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HMC704 input reference frequency

HMC704 is a PLL need a extern VCO(VCXO) chip. the datasheet gives the recommond minmum  reference frequency is 25MHz with the sinusoidal input or 0.5v/ns skew with square. but actually I want to multiply a 1MHz sine frequency to 100MHz, so is the HMC704 can be used for this  function? if not, is there any other chips that can substitude this chip? but phase noise about PLL should be concerned as the vital factor. I have an idea,but I don't know whether it is ok.that is if using a Schmitt trigger or comparator to shape 1MHz sine reference into a 1MHz square with skew larger than  0.5v/ns. And I search the comparator chips list ,find that chip DCMP582 meets the requirements.but I don't know how much the chip DCMP582 introduces the phase noise.is it much than 1MHz reference frequency as the PLL HMC704's input directly? if so.this method would lose its meaning.    does the low frequency PLL( such as below 1MHz) produce phase noise more than high frequency PLL (such as 100MHz)? if  the input reference is not 1MHz ,but 1KHz,what the PLL phase noise would  be?

thank you.

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  • Yes, I agree according to your equation if you have two choices with identical N multiples:

    1. 1MHz to 100MHz
    2. 10MHz to 1GHz

    Pick the lower frequency option, or in other words the lower Fpfd,  for best phase noise.

    For a given output frequency where you have the option of picking Fpfd the best phase noise is obtained by minimizing N and maximizing Fpfd.

    If you have a phase noise analyzer you can measure the AD8561 performance and enter this phase noise profile into ADISimPLL.  The tool will calculate the PLL output jitter.

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  • Yes, I agree according to your equation if you have two choices with identical N multiples:

    1. 1MHz to 100MHz
    2. 10MHz to 1GHz

    Pick the lower frequency option, or in other words the lower Fpfd,  for best phase noise.

    For a given output frequency where you have the option of picking Fpfd the best phase noise is obtained by minimizing N and maximizing Fpfd.

    If you have a phase noise analyzer you can measure the AD8561 performance and enter this phase noise profile into ADISimPLL.  The tool will calculate the PLL output jitter.

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