Post Go back to editing

HMC704 input reference frequency

HMC704 is a PLL need a extern VCO(VCXO) chip. the datasheet gives the recommond minmum  reference frequency is 25MHz with the sinusoidal input or 0.5v/ns skew with square. but actually I want to multiply a 1MHz sine frequency to 100MHz, so is the HMC704 can be used for this  function? if not, is there any other chips that can substitude this chip? but phase noise about PLL should be concerned as the vital factor. I have an idea,but I don't know whether it is ok.that is if using a Schmitt trigger or comparator to shape 1MHz sine reference into a 1MHz square with skew larger than  0.5v/ns. And I search the comparator chips list ,find that chip DCMP582 meets the requirements.but I don't know how much the chip DCMP582 introduces the phase noise.is it much than 1MHz reference frequency as the PLL HMC704's input directly? if so.this method would lose its meaning.    does the low frequency PLL( such as below 1MHz) produce phase noise more than high frequency PLL (such as 100MHz)? if  the input reference is not 1MHz ,but 1KHz,what the PLL phase noise would  be?

thank you.

  • Operating the HMC704 with sine reference below the recommended 25MHz was discussed in your other post at https://ez.analog.com/message/250985#comment-250985 .

    You will need to convert the 1MHz sine wave to a square wave but the ADCMP582 output driver does not meet the 0.5Vpp minimum input level for the HMC704 reference.

    For best performance run the PFD as high as possible since from Eq 1 in the HMC704 datasheet higher PFD rates (f_pd) reduce PLL noise floor.  If you convert the 2nd term in the equation into dB form the phase noise floor is:

    where FOM=-227 dBc/Hz and f is the output frequency.

    Increasing the PFD frequency from 1MHz to 100MHz improve the PLL phase noise floor by 20 dB.  Just be careful you must respect the minimum N requirement.  In fractional mode N>=20.  In integer mode N>=16.  For example with Fout=100MHz the maximum PFD frequency is 5Mhz in fractional-N mode.

  • Sorry for disturbing you again. I can not understand what you replied. I think the equation you give is not proper. when the frequency mutiple are the same,such as from 1MHz to 100MHz and 10MHz to 1GHz, the equation may discribed as:

    if the frequency multiple could not change,then the fpd should be reduce for acquiring a low PLL_floor. So I give  1MHz RF for input,rather than 10MHz.But  how to transfer 1MHz sine to square to cater for the HMC704 input frequency or slew rate requirement?I have confused for a long time.

    The solution I mentioned and you explained before  was not the input level problem,but the difference to single-end problem, because HMC704 input reference just receives single-end. so would you please be much patient to help me to get a better method ,and I will be much appreciate. I know a comparator chip AD8561 can achieve this goal. but the datasheet does not give the jitter performance, So how to get the random jitter parameter of this chip? thank you.

    Best regards!

    Shang Ding .

  • Yes, I agree according to your equation if you have two choices with identical N multiples:

    1. 1MHz to 100MHz
    2. 10MHz to 1GHz

    Pick the lower frequency option, or in other words the lower Fpfd,  for best phase noise.

    For a given output frequency where you have the option of picking Fpfd the best phase noise is obtained by minimizing N and maximizing Fpfd.

    If you have a phase noise analyzer you can measure the AD8561 performance and enter this phase noise profile into ADISimPLL.  The tool will calculate the PLL output jitter.

  • Thank you.It is a pity that I  have no such condition. I am using a clock driver ADCLK905 for sharping 1MHz sinewave to get a high slew rate.I think this would be better .