I use HMC703 and HMC736
pfd=10M
RFout=14.75G
using frac mode
when i use adisimpll to simulate ,it can't lock
BW 40KHz
phase margin 60
how can i lock to my frequency
I use HMC703 and HMC736
pfd=10M
RFout=14.75G
using frac mode
when i use adisimpll to simulate ,it can't lock
BW 40KHz
phase margin 60
how can i lock to my frequency
ADISimPLL indicates a lock condition after about 160us but to see a decrease in phase error you must increase the simulation time to 350us. This is similar to your other post at HMC703+HMC632 .
