HMC778 Frequency Sweep Mode

Hi there,

The timing diagram shown in the datasheet shows that each step is synchronous with the internal divided VCO clock which is  but the trigger pulse is asynchronous. This means that there could be up to one PFD cycle before the first step is initiated. Since the trigger pulse is NOT synchronized internally with the PFD frequency there will some variability between this first step and the trigger edge each time a sweep is initiated depending on where the rising edge of the trigger pulse is with respect to the next rising edge of the PFD timing. We have not characterized this delay but have noticed that it can be on the order of a few hundred nS in some applications but there will be some variability in this depending on the customers layout and actual implementation.

After the sweep starts there will also be PLL settling time delay until the sweep starts a smooth ramp. Increasing the loop filter BW will reduce the PLL settling time delay but it can't be eliminated entirely. Finally, cycle slipping could also introduce unwanted delays so this feature may need to be enabled to refine the performance.

Ultimately your customer will need to figure out a way to synchronize the pulse sent to the TRIG pin with the internal@ REF / PFD frequency in order to eliminate the slight delay that may occur at the start of the ramp.

Best Regards,

Marty

Hi Marty

Thank you so much for your quick reply and detailed comments.
I will talk with the customer about your comments.
You've been very helpful.

Best Regards,