Inquiry about MUXOUT pin of ADF4113

My customer  has designed MUXOUT pin of PLL IC in digital lock detection mode, as shown below because of the difference in power level.

She was asked to comment of ADI on the design.

She has a problem that the muxout output is rarely high on unlock status of PLL.

Is there any problem as the above design ? If so, please explain why.

Thanks.

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