My customer has designed MUXOUT pin of PLL IC in digital lock detection mode, as shown below because of the difference in power level.
She was asked to comment of ADI on the design.
She has a problem that the muxout output is rarely high on unlock status of PLL.
Is there any problem as the above design ? If so, please explain why.
The Muxout output cannot drive much current. You show it driving about 30mA on your first figure, but less than 1mA on the second figure. I don't know about you, but low power logic can only drive a couple of mA. The datasheet shows the digital outputs at 0.5mA.