some questions about the simulation of HMC440  


 when i use HITTITE PLL DESIGN (v1.1) to simulate the loop filter of HMC440. i  find some questions.

Firstly, i simulate the loop filter of HMC440 in its datasheet . The schematic  just like below.

but the 3dB bandwidth of the simulation does not the same with the datasheet. The datasheet labels  the loop BW=1MHz. But my simulation is 2MHz. I don't know why. My simulation is in the enclosure.

Secondly, i calculate the loop filter by the formulas. And the PLL can lock .But the phase noise in the bandwidth is not

fit for the datasheet of hmc440. (the reference clock is ideal). So i want to know what's factor can affect the phase noise of the HMC440 and the loop filter. We use  the PFD filter firstly ,So we do not know which factor need to be carefully  handled.

Look forward for your reply

Thank you