I saw "AN-873" Application Note about structure of Lock Detect in PLL IC's ,I need this information about ADF4159. Is there similar Application Note for ADF4159 or Does this Application Note also applies to ADF4159?
App-note AN-873 does not apply to the ADF4159. The ADF4159 implements a digital lock detect. This circuit OR's together up and down outputs from the phase detector. Every 32nd pulse is measured and lock detect triggered when five consecutive pulses are less then a threshold set by "lock detect precision" stored in Reg 0x03. When Reg 0x03=1 all five pulse widths must be less than 6ns. When "0" the lock detector asserts lock when five consecutive measurements are less than 14ns. Lock remains asserted until any pulse width measurement is > 30ns or a Reg 0x00 write occurs.
Could you please let me know relation between "lock detect precision(LDP)" Reg 0x03 and "Loss of Lock (LOL)" Reg 0x03.
Is the following expected working ,
When LOL bit is 0 we see that on removing the REF we see no change to state of Digital Lock output .
When LOL bit is 1 we see that on Removing the REF we see output state changes to loss of Lock.
With best regards and wishes
When LOL is enabled (Reg 3=1) the ADF4159 indicates an immediate loss of lock when no reference is present. LDP on the other hand sets the lock detector threshold to either 6ns or 14ns. The lock detector circuit OR's together up and down outputs from the phase detector. When five of these pulses are less then LDP the detector indicates lock.
LOL is Reg 3 not Reg 3.