Hello,
I would like to drive the HMC723LP3 inputs by a LVDS25 or a LVPECL buffer of a FPGA (Virtex 6).
The egressing data signal from the FPGA is a PPS (pulse per second, 10% duty cycle) signal and is not dc-balanced, so is my intention is to avoid AC-coupling.
Could you please tell me what you recommandations are for DC-coupling from LVDS25 or LVPECL drivers to the CML entries of the
HMC723LP3?
Best regards,