Please could you recommend an op amp and loop filter for an HMC3716 with a VCO operating near the maximum frequency of 1.3GHz, tuned for best integrated phase noise? Phase noise of the VCO is approximately:
The reference is very good so I think it is possible to ignore the phase noise contribution from the reference. The integration frequency range of interest is 40Hz to 40MHz.
Have you ever made a PLL with the HMC3716 operating at 1.3GHz?
Your loop BW needs to be as wide as possible to get the best integrated noise. I know the LT6200 has successfully been used with our PLL products utilizing a PFD output to achieve a 700kHz loop BW, probably could be pushed further.
Use the link below to access an app note on how to synthesize the loop for this part using the legacy HMC PLL Design software. Long term this capability (PFD Filter) will likely be added to ADISimPLL.
Using the HMC PLL Design Tool for Synthesizers with a PFD output
FAQ: HMC Phase Frequency Detectors