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ADF4118 - 1MHz reference input

good morning everyone, i'm having trouble working with a reference input of 1MHz with the ADF4118.

i'm using an evaluation board (EVAL-ADF411XEBZ1) and a custom board i designed and i'm getting the same behavior (i suspect that i'm making a mistake that i can't recognize).

both boards have an ADI ADF4118 and a Sirenza VCO190-2453T.

loop filter has been designed choosing 200kHz of PFD frequency and 20kHz of loop bandwidth for a reference input signal of 1MHz and an output signal of 2453MHz. (Vcp = Vvco = 5V, Vdd = 3V)

in this particular test my interest is lowest phase noise and driving the reference input from an FPGA.

my measurement setup comprises a 3GHz oscilloscope, 2 vector signal generators (VSG), 1 vector signal analyzer (VSA) and 1 abritrary waveform generator (AWG): they share a daisy chained 10MHz reference so that they are all synchronized.

if i take a 100MHz sinusoidal signal from one of the VSG to the reference input of the boards, the output is excellent in the VSA and i can even compare it in time domain with the output (2453MHz) of the other VSG, having them perfectly sinchronized in frequency and phase on the oscilloscope.

if i take a 1MHz square signal from the AWG to the reference input of the boards, the output is more noisy in the VSA (like if a light phase modulation is occurring) and in fact it can not be compared it in time domain with the output (2453MHz) of the VSG, since one waveform has kind of a phase drift in time with respect to the other.

however, if i take the 1MHz square signal from the AWG as the clock of an FPGA and take out the same signal from its GPIO header, the output is even more noisy, with two spurs spawning at the sides of the center frequency (this is really strange since the signal from the fpga is even sharper in its edges if compared to the one from the arb, it has more ringing though).

of course if i compare the outputs of two boards sharing the same reference input somehow, they are always "locked" in time domain ... the comparison with the VSG output is "unfair" with such a low frequency reference signal?

i'm starting to think that i'm making some mistake inside ADISIMPLL or with the device register configuration ...

once again, with a precise sinusoidal reference signal of 100MHz everything is working perfectly.

on monday i'll add figures from the VSA ... sorry about their lack now.

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