What is the frequency of the ring oscilator for lock detect in the HMC765?

We are having issues with LD remaining high consistently at  cold operating temperature.  I believe we are running all defaults in the LKD/CSP register 20.9

 

I see there is an option to use a ring oscillator for LD with a 3 bit callout for one shot duration.  Bits 16:14 active only if bit 13 is high.

 

I don’t see any timing reference of what the relative durations are for this type of LD.  Is there a nsec value for each bit in this 3 bit word?

 

Does bit 19 also need to be set to 1 for this to work?

Also saw:

How to choose the adjust the One-Shot Duration when using the Digital Ring Oscillator One-Shot:

Register 7 Bits[18:17] control the frequency of the Ring Oscillator.

Register 7 Bits[16:14] control the pulse width which is comprised of a number of cycles of the

Ring Oscillator (ranging from 0.5 to 64 cycles of the Ring Oscillator).

But nowhere do I see an even approximate value of the ring oscillator frequency.

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  • We tried your settings, and it did not work.  My original thought was that  = 0b  was 21 per the table with a divide by of four, yielding 5.5 nsec.

    I am thinking this did not work because it this actually sets the lock window to 21 nsec, and should be 5.0.

    But if this is true, why are there 8 columns for the ring oscillator speed?

    There are 32 separate speed listings in the table above from 6.5 to 338 nsec and 5 bits to set it.  2 to the fifth power is 32.

    If the top number is just the ring oscillator period, you would need other bits to set the divide ratio.

    It appears to me that the table accounts for the divider value with the number above.  Thus the lowest absolute value is 6.5 with 18:14 set to zero.  If the top line is looked at

    6.5         8.0         11           17           29           53           100        195

    8.0 =6.5 x 1.23

    11= 8 * 1.375

    17=11* 1.545

    29=17 * 1.7

    53= 29.1.82

    100 = 53*1.89

    195= 100 *1.95

    Looks like the divider is built into the table, thus 6.5 nsec is closest to 5 nsec.

    If the divider is built into a portion of the ring oscillator, the frequency would not quite double for each successive /2.

    Is 6.5 nsec actually the actual closest to 5.0 nsec using all zeros for bits ?

    attachments.zip
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  • We tried your settings, and it did not work.  My original thought was that  = 0b  was 21 per the table with a divide by of four, yielding 5.5 nsec.

    I am thinking this did not work because it this actually sets the lock window to 21 nsec, and should be 5.0.

    But if this is true, why are there 8 columns for the ring oscillator speed?

    There are 32 separate speed listings in the table above from 6.5 to 338 nsec and 5 bits to set it.  2 to the fifth power is 32.

    If the top number is just the ring oscillator period, you would need other bits to set the divide ratio.

    It appears to me that the table accounts for the divider value with the number above.  Thus the lowest absolute value is 6.5 with 18:14 set to zero.  If the top line is looked at

    6.5         8.0         11           17           29           53           100        195

    8.0 =6.5 x 1.23

    11= 8 * 1.375

    17=11* 1.545

    29=17 * 1.7

    53= 29.1.82

    100 = 53*1.89

    195= 100 *1.95

    Looks like the divider is built into the table, thus 6.5 nsec is closest to 5 nsec.

    If the divider is built into a portion of the ring oscillator, the frequency would not quite double for each successive /2.

    Is 6.5 nsec actually the actual closest to 5.0 nsec using all zeros for bits ?

    attachments.zip
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