What is the frequency of the ring oscilator for lock detect in the HMC765?

We are having issues with LD remaining high consistently at  cold operating temperature.  I believe we are running all defaults in the LKD/CSP register 20.9

 

I see there is an option to use a ring oscillator for LD with a 3 bit callout for one shot duration.  Bits 16:14 active only if bit 13 is high.

 

I don’t see any timing reference of what the relative durations are for this type of LD.  Is there a nsec value for each bit in this 3 bit word?

 

Does bit 19 also need to be set to 1 for this to work?

Also saw:

How to choose the adjust the One-Shot Duration when using the Digital Ring Oscillator One-Shot:

Register 7 Bits[18:17] control the frequency of the Ring Oscillator.

Register 7 Bits[16:14] control the pulse width which is comprised of a number of cycles of the

Ring Oscillator (ranging from 0.5 to 64 cycles of the Ring Oscillator).

But nowhere do I see an even approximate value of the ring oscillator frequency.

Parents
  • We are using a 100 MHz reference and locking at a fixed frequency of 8 GHz with the HMC765.  You suggest: We recommend setting the lock window mid-way between the minimum (set by offset current) and the maximum (set by the reference period).

    We are in integer mode, thus offset is set to zero.  Per HMC700 FAQ: In Integer Mode, both CP Up & Dn Leakage (Offset) must be 0 otherwise phase noise

    performance will be degraded.

    Thus we would ½ the reference period.  Reference period = 10 nsec, ½ of that = 5 nsec.  We are currently using the default lock detect window of +/- 10 nsec which is the same as the reference frequency.  Depending upon the methodology of how the pulses are compared to determine lock, I can see where this might not work.  (apparently in our case it reports lock except at cold frequency)

    After reviewing the PLLs WITH INTEGRATED VCO - MICROWAVE APPLICATIONS

    PRODUCT & OPERATING GUIDE:  I see the example comparison frequency is the same, 100 MHz, and the required pulse width is 2.6 nsec.  Which brings me back to my original question for the HMC765, what is the frequency of the ring oscillator?  We are using an HMC765, not using an HMC700 so we can’t view test pin 6, not sure if there is an equivalent pin on the HMC765.  I need instruction on how to set the pulse width for lock detect to 2.6 nsec on the HMC765, assuming the below is correct.

    When operating in Integer Mode, the required LD pulse width must be less than the reference

    period. 20% of the reference period is recommended.

    Example 2: 100MHz comparison frequency, Integer Mode:

    Required pulse width=  x 0.2 x 1.3 = 2.6ns

    This value is significantly less than the default 10ns pulse width.

    How to choose the adjust the One-Shot Duration when using the Digital Ring Oscillator One-Shot:

    Register 7 Bits[18:17] control the frequency of the Ring Oscillator.

    Register 7 Bits[16:14] control the pulse width which is comprised of a number of cycles of the

    Ring Oscillator (ranging from 0.5 to 64 cycles of the Ring Oscillator).

    The Digital One-Shot pulse width can be observed on the test pin # 6 of the HMC700 by using the

    GPO test feature (Register D Bits[3:0]=5h and enable the GPO Pads Register 8 Bit[5]=1)).

    As pin # 6 is observed on an oscilloscope the pulse width can be changed by programming

    Register 7 Bits[16:14] and Bits[18:17]

    Note: I am fairly certain we are using a reference divider of 1 and a VCO /80.  (I am checking with the original designer)  In any case we are clearly in integer mode.

Reply
  • We are using a 100 MHz reference and locking at a fixed frequency of 8 GHz with the HMC765.  You suggest: We recommend setting the lock window mid-way between the minimum (set by offset current) and the maximum (set by the reference period).

    We are in integer mode, thus offset is set to zero.  Per HMC700 FAQ: In Integer Mode, both CP Up & Dn Leakage (Offset) must be 0 otherwise phase noise

    performance will be degraded.

    Thus we would ½ the reference period.  Reference period = 10 nsec, ½ of that = 5 nsec.  We are currently using the default lock detect window of +/- 10 nsec which is the same as the reference frequency.  Depending upon the methodology of how the pulses are compared to determine lock, I can see where this might not work.  (apparently in our case it reports lock except at cold frequency)

    After reviewing the PLLs WITH INTEGRATED VCO - MICROWAVE APPLICATIONS

    PRODUCT & OPERATING GUIDE:  I see the example comparison frequency is the same, 100 MHz, and the required pulse width is 2.6 nsec.  Which brings me back to my original question for the HMC765, what is the frequency of the ring oscillator?  We are using an HMC765, not using an HMC700 so we can’t view test pin 6, not sure if there is an equivalent pin on the HMC765.  I need instruction on how to set the pulse width for lock detect to 2.6 nsec on the HMC765, assuming the below is correct.

    When operating in Integer Mode, the required LD pulse width must be less than the reference

    period. 20% of the reference period is recommended.

    Example 2: 100MHz comparison frequency, Integer Mode:

    Required pulse width=  x 0.2 x 1.3 = 2.6ns

    This value is significantly less than the default 10ns pulse width.

    How to choose the adjust the One-Shot Duration when using the Digital Ring Oscillator One-Shot:

    Register 7 Bits[18:17] control the frequency of the Ring Oscillator.

    Register 7 Bits[16:14] control the pulse width which is comprised of a number of cycles of the

    Ring Oscillator (ranging from 0.5 to 64 cycles of the Ring Oscillator).

    The Digital One-Shot pulse width can be observed on the test pin # 6 of the HMC700 by using the

    GPO test feature (Register D Bits[3:0]=5h and enable the GPO Pads Register 8 Bit[5]=1)).

    As pin # 6 is observed on an oscilloscope the pulse width can be changed by programming

    Register 7 Bits[16:14] and Bits[18:17]

    Note: I am fairly certain we are using a reference divider of 1 and a VCO /80.  (I am checking with the original designer)  In any case we are clearly in integer mode.

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