HMC659 biasing sequence

Hello,

In case that Vgg1 is pre-adjusted and fixed by register divider, is following sequence no problem?

The biasing sequence:
A) Set Vgg1 (Idq adjusted voltage, fixed to somewhere between -2V and 0V)
B) Set Vdd to +8V
C) Set Vgg2 to +3V
Timing: A)<B)=<C)

My customer understands recommended biasing sequence described in https://ez.analog.com/docs/DOC-11963, however, from circuit size point of view they would like to apply fixed voltage to Vgg1 by resister divider.

Best Regards,

Parents
  • In general there are 2 types. The cascode ones have a positive Vgg2 requirement, like the one you asked above. We have not tested them but we do not expect any issues with following the same sequence for them.

    The second type are not cascode, so Vgg1 and Vgg2 are for different amplifier stages and they are both negative. They can be tied together, or at some cases either one of them can be used.

    We started putting power up and down sequence for the newly released parts so it would be easier for user to operate the device.

Reply
  • In general there are 2 types. The cascode ones have a positive Vgg2 requirement, like the one you asked above. We have not tested them but we do not expect any issues with following the same sequence for them.

    The second type are not cascode, so Vgg1 and Vgg2 are for different amplifier stages and they are both negative. They can be tied together, or at some cases either one of them can be used.

    We started putting power up and down sequence for the newly released parts so it would be easier for user to operate the device.

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