ADF41020

Hello,

I want to simulate with ADIsimPLL the ADF41020 circuit to generate a 12.25 GHz signal. I set the PFD at 50 MHz but there is an error given by ADIsimPLL as you can see here.

I really don't understand why it is not working. I think that the divider can't reach the value of 12.25 GHz/50MHz =  245, but i'm not sure.

Yours 

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    •  Analog Employees 
    on Aug 2, 2018 3:48 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin
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  • 0
    •  Analog Employees 
    on Aug 2, 2018 3:48 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
    EZ Admin
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