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I want to simulate with ADIsimPLL the ADF41020 circuit to generate a 12.25 GHz signal. I set the PFD at 50 MHz but there is an error given by ADIsimPLL as you can see here.

I really don't understand why it is not working. I think that the divider can't reach the value of 12.25 GHz/50MHz =  245, but i'm not sure.


  • The ADF41020 has a fixed divide-by-4, so the N-value must be divisible by 4


  • Thank you PeterW,

    But i try to generate a 12.4 GHz signal , so N = 12.4 / 0.05 = 248 and it is still not working. 248 is divisible by 4 .

    Can you help me please ?


  • You are right that 248 = 4 x 62, so it passes the divide-by-4 requirement, but the rest of the N counter still has to achieve the remaining 62, and as the information panel tells you, you can't use the P=8 prescaler as it will violate the max prescaler output frequency requirement, so you will have to use the P=16 prescaler, and this cannot achieve the desired value of 62.

  • Buried at the bottom of page 11 of the datasheet is:

    so 62 is not achievable as B=3, A=14 does not satisfy B >= A.

    This is due to the way the P/P+1 prescaler works. If it was just a fixed /16 prescaler you would only get multiples of 16. So, for example, to get 48 you would set the following divider to 3, but you couldn't get 49. Using a 16/17 prescaler and setting the subsequent divider to 3 (B=3), you get 48 by never dividing by 17 (A=0), you can get 49 by dividing by 17 for one cycle (A=1), and then by 16 for the next two, you get 50 by dividing by 17 for two cycles (A=2) and then by 16 once, you get 51 by dividing by 17 for all three B cycles, but you can't get 52 as you want to divide by 17 for 4 cycles but you only have 3. This is why B >= A is needed. 

    It is done this way to avoid the whole counter having to run at the input frequency. For more information search for pulse swallowing divider.

  • Thank you for you answer,

    But for the remaining 62 , it has to be achieved by ( BP + A ). So if P = 16 , B and A could be set at 3 and 14, respectively. 16 * 3 +14 = 62, i don't understand why it cannot achieve this value.


  • Thank you very much for your answer PeterW .

    I have an other question, but it is not in the same subject ( but still RF and Microwave).

    I want to reduce the jitter  I get from a PLL, does the phase jitter with carrier recovery reduce the Jitter ( in degree rms ) ?

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