I designed a PLL with the HMC439QS16GE for synthesizing FMCW signal ( 45 - 57.5 MHz -> 720 - 920 MHz)
When I design the PLL, I referred 'Typical PLL Application Circuit' in the datasheet of the HMC439QS16GE.
Different things are VCO and Dividers. The VCO is ROS-1700W from Mini-Circuits, and Dividers are HMC365S8GE (Divide by 4, twice. So, total 16-division)
I tested with input signal of 50 MHz (sinewave 1Vpp, no DC offset)
However, I failed to lock the input signal.
I think there's no problem in Loop filter, VCO, and dividers.
The thing that bothers me is output of the HMC439QS16GE.
When the input signal is aforementioned 50 MHz, the output of dividers is now around 42 MHz (this signal is applied to VCO pin of the HMC439QS16GE). Then, I think that the output voltage on the NU pin should be smaller than the voltage on the ND pin, because the tuning voltage of the VCO should be increased to make more higher frequency. (The input of the differential and integral op-amp is (V+)-(V-), and this becomes (ND)-(NU) according to the datasheet) However, the NU is larger than ND now !
I've tried with another HMC365S8GE, but results were same.
I also tested with the input of 100 MHz, but NU is still larger than ND.
What are problems ? and how can I handle these ?
I really want to operate my PLL.
PLEASE HELP !
p.s. By the way, the interface schematics of REF(3) and VCO(6) pin are same, but why is there voltage(around 3.4 V) only on the pin R ?
So if I understand you correctly the ROS-1700W (770MHz - 1700MHzm, Vtune = 1-24V) is being used from 720MHz (Vtune ~ 1Vdc) to 920MHz (Vtune ~5Vdc). This is divided down by 16 using (2) HMC365S8G divide-by-4 devices to yield frequencies ranging from 45MHz to 57.5MHz into the phase detector VCO input.
These frequencies are being compared to a 50MHz reference.
The reason that you can't achieve phase lock is that the HMC439 is an integer-N, phase frequency detector so the only frequency that I would expect to lock using a 50MHz reference would be when the VCO is set to 800MHz (or 1600MHz if a 100MHz reference were used).
In other words, the input to the Reference port (pin 3) and the VCO port (pin 6) must be at the same frequency in order to lock. 920MHz / 16 = 57.5MHz which is a fractional value so unless the reference is changed to 57.5MHz it's not going to lock (or if you can divide by 18.4 somehow).
You might want to consider using the HMC703 PLL for FMCW applications due to it's fractional capability and its sweep / ramp functions .