for a custom board I am using the the HMC6300/01 chips and was wondering if there exist any special programming order for the registres. So far I haven't found anything about it in the manual or here in the discussions.so do I just start from Register 0-23?
And what I still don't get, how is it possible to send 8 bits over SPI and deassert the CS in the middle of the process (after 2-Bits). Normally I do this kind of transmission with DMA. So there is no possibility to stop after a non 8-Bit related transfer.
Since I use an STM32 for the SPI acces It is possible to set the payload in 9-Bits and I hope this will work.
I started writing my own program to control the HMC6350 since the available software refused to work in a state for the art windows and I gave up playing with the compatibility settings after 2 days. I can not post the code here but it is relatively easy to use the FTDI D2xx driver, set the FT2232 in synchronous bit bang mode and send a byte stream with the required pattern. However, I'd like to post my solution on the SPI obstacles.
The IC reset is high active. The SPI does not answer when this pin is high. I have not reengineered so far what setting is in the registers after RESET. On the first glance it seems to be all zero.
1) the write access
Datasheet Rev B is misleading, Rev C is correct with regards to the positive edge. As written in the text change data when clock is low and send the positive/rising edge when data is stable.
I'd like to call the rows registers and the chip has 32 of them where 0..27 is used and 0..23 is writable. This requires 5 address bits and as far as I could see the MSB (No.13 in Figure17 is ignored)
Not sure what the chip address is for but for me it worked when I considered it as a 6 with an LSB of 0 at bit 15 and 11 at position 16 and 17.
I did set ENABLE high after the last falling clock edge and it was working and this seems to me reasonable for a typical SPI interface.
2) the read access
If you observe the data lines with a logic analyzer you will see output signal echoes from the previous access when you shift in the dummy data and address. If you do not see anything on your data line check your connection and if RESET is inactive.
I did the intermediate ENABLE=high with a clock in between. This seems required.
As far as I could see, the chip does not provide useful read data in the 2nd ENABLE-Phase when your chip address is not 6.
Other than drawn in Figure 18 I saw the IC changing the read data with the positive edge and the data was stable with the falling edge. For the FTDI this is not an issue since the received data stream contains data for both edges. For most SPI-Systems this may also work since the clock on the master side is ahead of the data returning from the slave and the turnaround may generate enough hold time for the master to read the data.
I hope this is a useful info snippet. Regards, Thomas.