ADF4355-3 programming.

Hello. Could someone answer the following about the ADF4355-3 synthesizer:

1. If I want to use software power down mode after I programmed the IC, is there a register sequence to get back to power on mode or do I just flip the bit back? Is it possible to run the initialization described on page 29 of the datasheet with the power down bit set, i.e. initialize into power down mode?

2. What are the guidelines for setting the timeout in register 9? The programming tool sets it to 32. There is no explanation why. What is this timeout used for?

3. What are the guidelines for setting Fractional-N Lock Detect Count? The tool sets it to 4096 by default.

4. What is the meaning of the Fractional-N Lock Detect Precision setting?

Thanks in advance.

  • 0
    •  Analog Employees 
    on Jul 4, 2017 5:39 PM

    > Hello. Could someone answer the following about the ADF4355-3
    > synthesizer:
    >
    > 1. If I want to use software power down mode after I programmed the
    >    IC, is there a register sequence to get back to power on mode or
    >    do I just flip the bit back? Is it possible to run the
    >    initialization described on page 29 of the datasheet with the
    >    power down bit set, i.e. initialize into power down mode?

    Initialization cannot be done in power down mode.

    If you use software power-down then it doesn't wipe the register contents.  The register remain at the values they were at before.  You need to re-acquire though which means re-writing the "trigger registers".  That means you need to write R10 to start a temperature read.  Then when that's finished you need to write R0 to trigger reacquisition.

    So, it's like the frequency update sequence on p.30 of the datasheet except you don't need to write R1 or R2.  If time isn't a problem you may as well do the normal frequency update sequence.

    > 2. What are the guidelines for setting the timeout in register 9?
    > The programming tool sets it to 32. There is no explanation
    > why. What is this timeout used for?

    It gives the following equation on p.27:

    Synthesizer Lock Timeout > (20 μs × fPFD) / Timeout

    Perhaps it's clearer to write it like this:

    Delay = (Synthesizer Lock Timeout * Timeout) / fPFD

    This is just a rearrangement of the above.

    So, let's say that the PFD frequency is 50MHz.  We need the inverse of that which is a time, 2e-8, or 20ns.  So, if Synth-Lock-Timeout and Timeout are both 1 then the delay will be 20ns.  Now, you need to set Synth-Lock-Timeout and Timeout so they multiply together to give you a delay longer than 20us.  In this case you could set Synth-Lock-Timeout to 11 and Timeout to 100, that would work.  You could also do the same by setting Synth-Lock-Timeout to 21 and timeout to 50.

    (11 * 100) * 20ns = 22us.
    (21 * 50) * 20ns = 21us.

    (You may wonder why we have the two factors Synth-Lock-Timeout and Timeout.  If you look at the datasheets for the other ADF4355 family parts they explain it.  On those there's another timeout calculation that uses the factor "Timeout".  This extra timeout, the ALC timeout, doesn't apply to the ADF4355-3.)

    > 3. What are the guidelines for setting Fractional-N Lock Detect
    > Count? The tool sets it to 4096 by default.

    For 99% of applications you can leave this on the default of 4096.

    The lock-detect circuit is composed of two parts.  Firstly, there's a circuit that is continuously detecting lock.  This circuit gives a true or false for every PFD cycle.  Of course, in some cases the part may be close to lock by chance.  So, we can't rely on this circuit by itself.  To supplement it the part counts positives for a certain number of cycles.  That's what this setting controls.  So, if you set it to 4096 that means the part must see that lock=true for 4096 PFD cycles.  Only after seeing 4096 subsequent trues will it raise the lock-detect line high.

    So, this is the trade-off.  If you count more cycles then there is less chance of a false-positive, there's less chance that the Muxout/lock-detect pin will report lock when it hasn't happened.  If you count fewer cycles then the part responds faster and lock-detect goes high faster.

    By default we set it to 4096 which is a high value, this prevents false-positives.  Some customers reduce this because lock-time is very important to them.  If you don't care about lock-time then I recommend leaving it alone.

    > 4. What is the meaning of the Fractional-N Lock Detect Precision
    > setting?

    As I said above, there's a circuit that's continuously detecting lock.  It uses the signals from the PFD; the up and down signals.  If the part is locked then only very small adjustments are needed.  So, in each cycle PFD cycle the up or down signal will be on for a very short amount of time.  So, we set a window time in nanoseconds.  If the up or down signal is high for more than the window time then the loop is deemed to be unlocked.  The two settings Lock-Detect-Mode(LDM) and Lock-Detect-Precision(LDP) control this.

    As it says in the datasheet if you're using Integer-N mode and you have bleed turned off then you can set Lock-Detect-Mode to 1.  That will make the window time 2.9ns.  This short window can detect lock in this situation.  If you're in Frac-N mode and you have bleed on then you should set the window much wider: LDM=0 and LDP=12ns.  The datasheet tells you to turn on bleed in Frac-N mode, that gives better phase noise.  If you follow that then you should always use LDP=12ns in Frac-N mode.

    There are some situations where people want to use the other LDP settings, but they're not common.


    We should mention more of this on the datasheet.

  • Hi,

    Here are some questions about ADF4356.

    1,When there is no REF clock input, it can also generate a RF output, but the frequency is not correct.

    2, The Creg1 pin(pin25) has no voltage output,the Creg2(pin 32) output voltage is 1.89V. But in the datasheet, the norminal voltage is 1.8V.  Is this chip OK? Or is it damaged?

    3,In addition, in the other almost identical circuit, the ADF4356 has no Creg1 output either, but it seems that it works well.

     

    Can you give me any advices? Thanks.

  • Hi Rob. Could you also help with Register 12 settings? I read the explanation of how to set bits [31:16] but it's still not clear. Let's say my lock time is 200uS. How would you set the phase resync clock? The programming software for the ADF4355 reference design defaults to 1. Thanks.