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HMC924LC5 Vgg and Vdd2,3,4 control


    We are using the HMC924 in our design. As per the guidelines, Idd2 + 3 + 4 should be set to 170mA by tuning Vgg. 

In our case we tried setting Vgg to 0, -1, -2V and in all three cases the current being drawn is a lot. We set a bench top supply to provide 5V and 300mA (current limit) and the current being drawn is more than 300mA and so that voltage drops to about 0.35V. 

We have double checked our circuit (it is also attached to this post) and the soldering also seems fine. 

Please advise on how to debug the problem. 


  • Hi,
    The biasing procedure for the HMC924LC5 is as follows:
    1) Connect Vgg to a -2V power supply
    2) Connect VDD1 to a 5V power supply.
    3) Connect VDD2, VDD3 and VDD4 to a different 5V power supply.
    3) Adjust VGG between -2V to 0V until IDD2+ IDD3 + IDD4=170mA
    4) Turn on LO signal of +0dBm
    5) Turn on IF signal

    To turn off

    1) Turn off IF & LO signals
    2) Set VGG  to -2V
    3) Set VDD 1, VDD2, VDD3 and VDD 4 to 0V and then turn it off
    4) Turn off VGG supply

    The current specified in the datasheet is a quiescent current so when the LO is turned on the current draw is going to increase. The current limit of 300mA is probably too low.


  • Hello Mthahira,

             Thank you for your reply.

    May I ask you to please provide the resistances at the Vgg and Vdd2,3,4 pins so that we can check the connections using a multimeter. 

    We are not seeing any variation in the Vdd2,3,4 currents as the gate voltage is changed.


  • Hello,

         May I also you to please help us understand the conversion gain numbers for the HMC924LC5.

    As per the datasheet: for operation between 13 to 16GHz, the CG is 15dB (I assume this is at maximum Vctrl of 2V)

    Does this mean that for an input of -6dBm the output will be at 9dBm (with a 3dB hybrid) and 6dBm without the 3dB hybrid?

    Also, the LO to RF rejection is mentioned at 15dB with respect to the desired RF signal level. So in the case where the RF signal is at 9dBm, the LO level will be 9 - 15 = -6dBm. 

    We are seeing something different, we set Vctrl to -1V (CG of about 1dB) and IF 10MHz  at -6dBm. We were expecting to see the output at -5dBm but instead it is at -25dBm.

    The input LO level is 4dBm and we are seeing the LO leakage at the output at -4dBm. 

    Please guide us,


  • Hi,

    The resistance for these pins were measured at ambient without the part turned on:

    Vdd2=20 ohms

    Vdd3= 10ohms

    Vdd4 =5 ohms

    Vgg= >5 M ohms (expected as this is the gate)

    If the Idd 2+3+4 does not change with Vgg then its most likely that this part is damaged. The HMC924LC5 is susceptible to damage if the correct bias procedure is not followed. Since this part is now obsolete we do not sell anymore eval boards and do not encourage it for new designs. The recommended part is ADRF6780. 

    In terms of your second question: 

       If you put in -6dBm at the 90 degree hybrid input (with hybrid loss calibrated out) then the output power of HMC924LC5 at max gain (VCTRL=-2V) would be around 9dBm.  The 90 degree hybrid acts like a quadrature power splitter. If the hybrid is ideal-no loss- then the  power at IF1 and IF2 would be -9dBm each. Usually hybrids will have some loss- example 1dB- then the power at IF1 and IF2 would be -10dBm each. This means the total input power is -7dBm and the output power at the RF port would be 8dBm.

    For your third question:

     Are you driving the part as quadrature (I.e quadrature signal at 10MHz for IF1 and IF2)? What is the output power at the other sideband?