Hello,
we are using the HMC394 5-bit counter in a clock synthesizer application.
The counter is set to divide by 20. The measured Phase Noise Floor from about 100 kHz to 10 MHz is -140 dBc/Hz with a clean input signal. We need it about 15 dB better, as indicated in the datasheet. What can be the reason for the poor noise floor?
Best Regards,
tom