we are using the HMC394 5-bit counter in a clock synthesizer application.
The counter is set to divide by 20. The measured Phase Noise Floor from about 100 kHz to 10 MHz is -140 dBc/Hz with a clean input signal. We need it about 15 dB better, as indicated in the datasheet. What can be the reason for the poor noise floor?
A colleague of mine that previously supported these dividers mentioned that he encountered this issue for a divide-by-10 case on this same device. It turns out to that due to the duty cycle, the phase noise of each leg of the differential pair is not equal. The leg that is "on" for longer periods of time will have degraded phase noise vs. the leg the that is "off". This same concept applies to the HMC Integer-N PFD products like the HMC439 and HMC3716.
Did you measure the phase noise on both outputs?
dmailloux Thank You
Interesting note about the HMC3716. We're planning to use this device for an ultra low phase noise synthesizer. What does that mean for this application? Under which conditions will the diff pair be in such an imbalance that the phase noise increases?
Thank you in advance,