HMC840 and HMC829 rapid frequency hopping

We are using HMC840 and HMC829 devices, both with 100 MHz phase detection frequency (PDF). We need to perform frequency hopping (in a range of about 100 MHz) and do it as fast as possible (preferably less than 100 usec.).

I have the following questions:

1. According to Hittite FAQ (Frequently Asked Questions about Narrowband, Triband, Wideband RF PLL+VCO Clock Generation Products), section 6, the subsection titled "Does CP Offset Current affect locking behavior of the PLL", it is necessary to perform a delay while performing a frequency hop. Specifically it says "Delay settling time of the PLL". How can I estimate the necessary delay?

2. If I use manual VCO calibration (as opposed to auto-calibration), is it necessary to perform the manipulation with CP offset that is mentioned in item 1 above (including the associated delay) when performing a frequency hop? Is there a chance that the PLL will not lock If I do not perform that manipulation?

Note: until now we have used VCO auto-calibration and we had to perform the above manipulation, or else the PLL would occasionally fail to lock.

3. The AN titled "Frequency Hopping with Hittite PLL VCIs" section 5 provides detailed instructions on performing manual VCO calibration (I prefer using the direct LUT method). In section 5.1 it specifies modifications to normal PLL programming (Reg08h[8], Reg0Bh[18:17]). It is not clear to me when these values should be programmed. Specifically, should I program these values:

- Once during initialization?

- Once after disabling VCO auto-calibration (step 7 in Table 1)?

- At some other time(s)?

Note: the above register fields are not described in any way in the user guide (in particular Reg08h[8] is marked as reserved in the user guide).

4. The Above AN in section 5.1, Table 1, item 4 indicates that for the HMC840 the data that should be stored in the LUT is: "Reg10h x 2^8 + 5".

Does it mean that for the HMC840 (as opposed to HMC829) the code that should be written to VCO register 0[8:1] to effect manual VCO calibration for a given frequency is not the exact value that was read from PLL register 10h[7:0] after completed auto-calibration using that frequency, and instead should use that value + 5 counts?

Thanks,

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  • 0
    •  Analog Employees 
    on Oct 23, 2017 11:42 PM over 3 years ago

    I've addressed your questions below.

    1)  For comparison frequencies >80MHz turn off offset current to help achieve lock.  The amount of delay necessary before turning offset current back on is dependent on the loop filter.  We want to insure there is enough delay to insure all cycle slips have died away and the phase error has settled to within 30 degrees.  You can simulate the PLL response with ADIsimPLL under the "TimeDomain" tab. 

    2)  Manual calibration must follow the same procedure but the delay will be smaller since the PLL no longer requires any autocalibration time.

    3) Set Reg 08h[8]=1 and Reg 0Bh[18:17]=10b once during initialization.  Reg 08h[8]=0 resets the N divider on every frequency update.  Usually we want to do this but with fast frequency hopping applications it causes spurious emissions due to the rapid frequency changes.  With the reset turned off, set Reg 0Bh[18:17]=10b to restrict operation of the N-divider.  This prevents potential corruption of higher order N-divider bits.

    4) We want VCO_reg 0x00[8:1] = PLL Reg 0x10[7:0].  But any VCO register write requires indirect access through Reg 0x05 thus there is some extra bit manipulation required.   See section 5.7 in the Operating Guide on how to write VCO registers.

Reply
  • 0
    •  Analog Employees 
    on Oct 23, 2017 11:42 PM over 3 years ago

    I've addressed your questions below.

    1)  For comparison frequencies >80MHz turn off offset current to help achieve lock.  The amount of delay necessary before turning offset current back on is dependent on the loop filter.  We want to insure there is enough delay to insure all cycle slips have died away and the phase error has settled to within 30 degrees.  You can simulate the PLL response with ADIsimPLL under the "TimeDomain" tab. 

    2)  Manual calibration must follow the same procedure but the delay will be smaller since the PLL no longer requires any autocalibration time.

    3) Set Reg 08h[8]=1 and Reg 0Bh[18:17]=10b once during initialization.  Reg 08h[8]=0 resets the N divider on every frequency update.  Usually we want to do this but with fast frequency hopping applications it causes spurious emissions due to the rapid frequency changes.  With the reset turned off, set Reg 0Bh[18:17]=10b to restrict operation of the N-divider.  This prevents potential corruption of higher order N-divider bits.

    4) We want VCO_reg 0x00[8:1] = PLL Reg 0x10[7:0].  But any VCO register write requires indirect access through Reg 0x05 thus there is some extra bit manipulation required.   See section 5.7 in the Operating Guide on how to write VCO registers.

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