Programming ADF4106

Hello;

I can not get my PLL work, I believe it is because of not correctly programming ADF4106, please confirm the below words are correct for initiating and setting 1030 MHz. Here are the words I sent for initial setting after power up:

0x9F80E3

0x9F80E2

0x0000A0

0x002019

Here, I use a 40 MHz reference signal. I would like to observe the MOSI signal outputted through MISO (muxout) pin.

1) Yet, I could not achieve the 1030 MHz signal outputted. Instead, I achieve the highest VCO frequency available. Therefore it seems that the charge pump of my PLL does not lead the returned signal from VCO. I attached my PLL circuitry for reference. I use THS4031MFKB (OpAmp) from TI, which has a positive bias of +5V, negative bias of -3.3V and reference voltage of 1.4V. What do I do wrong?

2) Assuming that I will be achieving the 1030 MHz signal (locked), I think that I have to send 0x00201D word to set the frequency 1031 MHz, and wait for it is being locked. For returning back to 1030 MHz (I am not interested in any fast locking or jumping to previous frequency privileges), shall I send again 0x002019?

3) In my PCB, there is not any sequentially turn-on for bias. All my parts (PFD, OpAmp, VCO etc.) get energized at the same time. I hope it is not a problem, I believe it is not, please also verify that.

4) Lastly, maybe I shall be setting phase detector polarity to negative, although the default setting is positive. I also need a direction (or confirmation) on that too.

Thank you in advance for assisting me in above four items.

Regards,

Sinan ONAT

Setting_1030MHz.pll.zip
  • 0
    •  Analog Employees 
    on Nov 7, 2017 5:39 PM

    Hey Sinan,

    1) In terms of attempting to read the MOSI serial data from the MUXOUT pin, see the file attached on Serial Data output from ADI PLLs

    2) Yes, this is the correct method for changing output frequencies with this part. A write to the N counter is sufficient to change the output frequency

    3) Energising all supplies at the same time should not be a problem

    4) Having looked at your ADIsimPLL file attached, it seems you should have the phase detector polarity set to 'Negative' rather than the default value. This will mean from start-up you should try writing:

    0x9F8063

    0x9F8062

    0x0000A0

    0x002019

     

    And see if that will get your frequency locked

     

    If you are still having issues, there is an alternative way to initialise the PLL without using the initialisation latch, by only using the function latch. I will attach the document on how to do this if you want to give it a try

     

    Hopefully this is helpful to you,

     

    Kind Regards,

    Alex

  • Hello again;

    Thank you for your informative answers although I could not receive any attached documents.

    Unfortunately I could still not achieve locked 1030 MHz out of my PLL. Indeed, after the power up, I see a ~5 seconds long sweep from 970 MHz to 1080 MHz, which actually means that my PLL is able to cover all the allowed frequency range (up to the op-amp positive supply: +5V). However no word, including your suggesting lines, set this ADF4106. I checked the words (bit by bit) on the ADF4106 pins (CLK, MOSI and CS) on my PCB, they are well shaped and correct so as my cyrstal. It is also interesting that, through the MUXOUT pin, I can observe DVdd, DGND but I can not see the MISO signal at all. I mean, I just observe the noisy ripples around ground level (0VDC) at the instants of MOSI signal is sent. It also supports my idea on this IC is not programmed correctly.

    I also tried to initialize the PLL by using the function latch (and then program with the last two lines of your suggestive words). It did not work either. Do you think that the lot we received are broken? Why do you think that the PLL is first sweeping and then stop in the highest op-amp supply limit? I see that it starts from 0V setting (of VCO) and ends up at 3.9V setting (of the VCO) which is the upper voltage output limit of the op-amp.

    As you saw my circuit, let me give more details on my op-amp. It is supplied by -5V and +5V, and the Vref is 2.7V, which is connected to the positive input. The negative input is connected to the CP of ADF4106 as stated in the suggested circuit by ADIsimPLL. I re-send the circuit snapshot below.

    Another important connection is the crystal. I use AST3TQ IC (by Abracon). It has a fixed 40 MHz LVCMOS output. I checked the levels and they are fine too.

    Regards,

    Sinan

  • Hello Alex;

    I had a chance to receive the documents you referred in your last comment. Thank you. They were useful.

    I believe it will be good to share you below two pictures, one is the schematic of the PLL and the other is the current measurements (Yellow: CLK, Blue: MOSI, Green: MISO / Muxout).

    Another thing is that, the LE signal is generally at Logic HIGH. However when (and during) a SPI word is being sent, it goes (and stay at) logic LOW. Once the data is completed LE becomes Logic High again. It is an usual SPI protocol, is not it? However, I did not get the Figure 3 on the Serial Data Output document you sent. My LE does not stay at Logic Low after the MOSI signal is sent, but yours seems to be staying low until the MISO (or MUXOUT) signal is received. How do you make that?

    Besides that, sometimes (but not always, that's also a big question of why?), I happen to be able to receive some pulse sequence on MUXOUT (MISO) as Figure 4. However it is weird that MUXOUT (MISO) signal is one clock ahead of the Data (MOSI) signal. How can that be happening? In any case, whether I observe the Figure 4 capture, my PLL still is not locking the frequency to 1030 MHz.

    You may see what I observe on the MISO (muxout) pin in general. It does not seem to be programmed (our outputted) well. I can measure and confirm that the input data is right (9F 80 63 9F 80 62 00 00 A0 00 20 19). And the LE is logic low only during the captured clock duration.

    Regards,

    Sinan

  • 0
    •  Analog Employees 
    on Nov 9, 2017 9:04 PM

    Hey Sinan,

    Thanks for the plots, 

    I do agree there seems to be some weird goings on with your Serial Data at the Muxout which I will need to look into. Setting the serial data aside for a moment, are you able to see N Divider and R Divider values at the Muxout?

    To read the N Divider at the Muxout try:

    0x9F80A3

    0x9F80A2

    0xA0

    0x2019

    and to read the R Divider try:

    0x9F80C3

    0x9F80C2

    0xA0

    0x2019

    Regards,

    Alex

  • Hello Alex;

    I am glad that you also agreed on its being weird. Did you have a chance to check my circuit? Is there anything wrong there (in the schematic design)? Please note that C705 and C694 was replaced with 0-ohm for keeping the LVCMOS shape as it is. The Op-Amp-Ref is 0.3V, which is the value advised by its manufacturer. The one thing I am suspicious about is CE is being logic high since the part is energized. Maybe that is a problem?

    Answer to your question is no, I do not see anything different (in neither N or R divider case). I attach the screenshot (Yellow: CLK, Green: CS / LE, Red: MuxOut, Blue: MISO / Data).   

     

    These are the measurements on the pins of ADF4106 and I checked the inputted data again, they are as you specified. You also may observe that it is the same response with the original setting (for input data out). That's why I think that no matter I send a control word, this IC reacts same. I simply can not program this IC, I guess. Maybe there is a connection problem (on the serial interface) in this IC, what is your opinion? Please also remember that I see the DVdd and DGND outputs from MUXOUT pins correctly, which means that this IC is programmed partly, somehow.

    Regards,

    Sinan