HMC981LP3E enable pin voltage

Hello,

I am using the HMC981LP3E bias controller to control the HMC8410LP2FE LNA and I am wondering if I can use a 1.8V GPIO to control the enable pin on the bias controller.  The datasheet stated that the minimum enable input threshold is 1.4V but there's no maximum threshold.

Also, if it's not too much trouble, can you do a sanity check on my schematic too?

Thanks,

-Andrew

attachments.zip
  • 0
    •  Analog Employees 
    on Nov 9, 2017 8:48 PM

    Hi Andrew,

    I support the HMC8410LP2FE.

    There are a few things in your schematic that I recommend changing. In fact, the changes I recommend are likely related to the fact that the current revision of our data sheet (Rev. 0) contains disagreement between the Figure 37 Typical Application Circuit (TAC) and the Figure 39 Evaluation Board Schematic (EBS). Your schematic more closely resembles the TAC, but the TAC is wrong. What we actually measured for the data sheet is the evaluation board, so the EBS is the correct schematic and the one you should follow. You should change your schematic to match the EBS. Our TAC also shows C13 (a polarized cap) oriented incorrectly. Since VGG1 is a negative voltage, the positive terminal of C13 should connect to ground, not to the VGG1 line. I don't see polarization noted on your schematic, so I wanted to mention it so that you can keep it in mind for the polarized electrolytic caps.  

    Important: Because RFOUT is also the VDD pin, you will need to DC block the output signal before driving the next stage. This is shown as a 10 nF cap on the EBS, but is not included on your schematic.

    Data sheet Table 6 (the BoM) includes specific manufacturer name and part number info for several components. Those details were included to help customers select components that allow them to best match the data sheet performance in their application.

    Also, our data sheet incorrectly states the Derate factor for Continuous Power Dissipation in the Absolute Maximum Ratings table. It is incorrectly stated as 1.48 mW/deg C. The correct value is 14.8 mW/deg C. 

    Where our data sheet is wrong we have the items noted for correction on the next data sheet revision.

    Let me know if you have additional questions.

    Regards,

    SMcBride 

  • Hi SMcBride,

    Thank you for looking over my schematic.  I totally forgot the DC blocking capacitor.  I actually did follow the evaluation board schematic when I create my schematic.  Is there anything wrong with it that make you think I was following the typical application schematic?  Regarding C13, I am currently using a multi-layer ceramic capacitor.  Is that acceptable or do I have to use a polarized capacitor?

    Thanks,

    -Andrew

  • 0
    •  Analog Employees 
    on Nov 10, 2017 7:48 PM

    Hi Andrew,

    I thought you might have been following a combination of both the TAC and the EBS since your C197 was of value 4.7 uF (in agreement with the TAC though in disagreement with the 2.2 uF shown on the EBS), and since your C191=C196=0.1 uF=100 nF is in agreement with the EBS but in disagreement with the TAC. Just make sure to follow the values shown on the EBS.

    Our TAC and EBS disagree in their assignment of reference designators but, I assume the C13 to which you refer is the one from the TAC (4.7 uF). For both uF range caps (2.2 uF and 4.7 uF) you should find non-polarized ceramic caps to work fine.

    Regards,

    SMcBride 

  • 0
    •  Analog Employees 
    on Nov 10, 2017 8:27 PM

    Hi Andrew,

    Regarding HMC981LP3E ,

    The min high level for VEN is 1.4V, high is Vdig. So 1.8V is acceptable for High level.

    SCH looks ok. 487 Rsense is correct for 65mA. 5.65V is also correct, since for 65mA DUT Idd and 10ohm RDS_ON the bias controller drop will be 0.65V. By using R5,R39=1.6M, the min level Vgate hits during limited to -2V instead -2.5V, correct considering DUT AMR of -2V.

    Best,

    Kagan