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Multiple ADRF6720 output synchronization

Dear All

I have a board with 5 ADRF6720; the first is the master and generate the LOCAL signal (2x580MHz) and the other are slaves with the local passthrough as explained in the datasheet.

The clock supplied at each SSB are 28.6MHz and arrive to each with the same phase (PCB trace with same lenght). I want to output 433.92MHz Then I generate I and Q signal at the DDS at 146.08 MHz.

The I and Q signal for each ADRF6720 are perfectly in phase at DDSs outputs (between the 5 channel) but the RF output (after SSB) are not all in phase. Every each power-up they have randomly 0 degree or 180 degree each other.

I don't use polyphase and also I use 2x local distribution to avoid the 180° phase ambiguity as explained in the datasheet at page 20.

These are my configurations:

        --------------------- MASTER (generate LO) ---------------------------------

        0x0000,    //SOFT_RESET           {0}
        0xF77F,    //ENABLES                 {1}
        0x00A2,    //INT_DIV                    {2}  
        0x0352,    //FRAC_DIV                {3} 
        0x0DF7,    //MOD_DIV                 {4}  
        0xF000,    //ENBL_MASK            {5}
        0x0C26,    //CP_CTL                   {6}
        0x000A,    //PFD_CTL                 {7}
        0x0018,    //VCO_CTL                 {8}  
        0x00FF,    //BALUN_CTL               {9}
        0x1101,    //MOD_LIN_CTL          {10}
        0x0900,    //MOD_CTL0             {11}
        0x0020,    //MOD_CTL1             {12}
        0x0010,    //PFD_CP_CTL        {13}
        0x000E,    //DITH_CTL1            {14}
        0x0000,    //DITH_CTL2            {15}
        0x0000,    //VCO_CTL2             {16}
        0x14B0     //VCO_CTL3             {17}

        --------------------- SLAVES (are 4 slaves) ---------------------------------

        0x0000,    //SOFT_RESET     {0}
        0xF751,    //ENABLES           {1}
        0x0000,    //INT_DIV              {2}
        0x0000,    //FRAC_DIV          {3}
        0x0000,    //MOD_DIV           {4}
        0xF000,    //ENBL_MASK      {5}
        0x0C26,    //CP_CTL            {6}
        0x002A,    //PFD_CTL           {7}
        0x0004,    //VCO_CTL           {8} 
        0x00FF,    //BALUN_CTL         {9}
        0x1101,    //MOD_LIN_CTL    {10}
        0x0900,    //MOD_CTL0          {11}
        0x0000,    //MOD_CTL1          {12}
        0x0010,    //PFD_CP_CTL     {13}
        0x000E,    //DITH_CTL1         {14}
        0x0000,    //DITH_CTL2         {15}
        0x0000,    //VCO_CTL2          {16}
        0x14B0     //VCO_CTL3          {17}

any suggestion?

Regards

Piero

Parents
  • Hi Piero,

    Between ADRF6720 and ADRF6720-27 , the difference at requirement is mainly input common mode voltage at BB. And at -27, we extend operating frequency based on further characterization. However, this communication can cover both anyway. Refer to my comments.

    1. RF=433.92MHz

    The ADRF6720-27 can generate internal LO from 356.25MHz, but (for slaves) can accept external frequency LO from 700 400 to 3000MHz. This is the reason I use 2x LO output distribution.

       Tony] We specify 400MHz for the min external LO frequency for -27(700MHz for ADRF6720). So you can run -27 at 1xLO, 580MHz for your application. 

    2. 28.6MHz Clock for Reference(?)

    I connect it for furter different application, when the ADRF6720-27 are all master. I need to phisically disconnect when I use only one master? Cal trouble my application?

       Tony] Running ADRF6720-27 at slave mode with external LO, you don't have to disconnect the clock line physically since blocks and path are disabled and disconnected internally at external LO mode. However, it can be potentially spurious source coupled to DUT. So it would be better not to have any potential noise source near DUT. Maybe, put 0 ohm on the line near clock source, then install 0 ohm for all master application, not install 0 ohm for slave mode.

    3. 180° phase ambiguity 

    I'm not agree with your statement; at page 20 I understand 1x frequency LO has a phase ambiguity. In this case (1x) the datasheet suggests don't use the path after quadrature divider but use the second 1x path with the assertion of LO_DRV1X_EN bit.

    It's not specified, but I think 2x the frequency of the LO don't have phase ambiguity. Or It's wrong?

    Also I'm not be able to use 1x (then the polyphase filter) because 580MHz is less than 700MHz required for external LO.

    Tony] 2x LO itself doesn't have phase ambiguity but 1x LO from 2x LO path (#1 at my previous post) can have 180 deg phase ambiguity from div-by-2 on the path. And also running ADRF6720-27 with 2xLO  can give same phase ambiguity by Quad divider(div-by-2 for quadrature generation). Again, you are using ADR6720-27, not ADRF6720, specified Min LO on datasheet is 400MHz. So 580MHz is okay.  

    Thanks

    Tony

  • Hi Tony,

    The ADRF6720-27 data sheet Table 6 (page 19) says, as of Rev. B, that the external LO frequency ranges from 700 to 3000 MHz when using Polyphase quadrature generation. This contradicts the operating frequency range on Page 3 that correctly says 400-3000 MHz.

    Typo on page 19?

    Thanks!

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