Yes you can use a pure sine reference frequency but of course as the reference stage is a digital circuit, the counter will operate better with a sharper clocking edge (I.e. a better slew rate).
In other words, the phase noise performance of the PLL may be reduced when using a sine wave ref unless you can ensure the slew rate of the sine wave is good enough. To ensure this is the case you will have to use a higher drive level when using a sine wave than you would normally have to use if you were using a square wave. Typically for a sine wave ref the best phase noise performance occurs closer to upper end of the drive level. Although another caveat of using a sine wave ref is that you should bear in mind you may need to try various power levels particularly if you’re attempting to optimize for spurs
Thank you very much for your response.
I have an extra question about the drive level, you wrote:
To ensure this is the case you will have to use a higher drive level when using a sine wave than you would normally have to use if you were using a square wave. Typically for a sine wave ref the best phase noise performance occurs closer to upper end of the drive level.
From the datasheet I got this information:
So, if I am rigth, you advised me to input a sinewave signal with a level near to VDD volts peak-to-peak.
In other words when you refer to drive level, are you pointing to REFIN Input Sensitivity parameter?
Is this OK?
Thank you again.
Yep, the REFIN sensitivity is what I'm referring to. I would say it's worth trying a range of reference voltage levels below the max value of 0.8*VDD pk-pk to minimise spurs, but probably your phase noise response will be best when your REFIN pk-pk amplitudeis is close to the 0.8*VDD max value. Note this value is for a 50Ω AC coupled single ended reference, biased at VDD/2
Hope this helps,
Hi, I saw this thread and wanted to post my own question for the ADF4108. I'm troubleshooting a board that is using a 10MHz square wave input as the REFIN, AC coupled. On the input side of the cap the square wave is from a CMOS buffer and is perfectly square, 0 to 3.3V. On the PLL side the signal is still perfect square wave, but now the signal is slightly below 0V to slightly below +3.3V. If biased at Vdd/2 should basically be the same waveform correct? The issue we are seeing is 10MHz spurs on our output that is present only on some, but not all our boards, like a few out of a lot of assembled and tested boards. Was wondering if this signal phenomena could explain that?