Hello Engineer Zone experts,
If I could get your insights, what really limits the minimum clocking frequency of the HMC760 and HMC661? Is it just the hold-mode droop rate limiting their output to a maximum recommended hold time of 2ns or is there some other internal clock dependent process in those devices that needs a 250MHz minimum refresh rate regardless of the hold mode droop rate?
The reason I ask is for applications like an equivalent time sampling oscilloscope front end it would be nice to be able to use the high-bandwidth of the HMC661 sample and hold, but followed with a lower sampling rate ADC to benefit from improved ADC performance and reduced data rates when 250MSPS+ are not required for the application.
If the only rate limiter of the HMC661 is the 2ns max output hold mode time, then why couldn't a lower speed ADC that simply has a suitably short internal track and hold aperture time (or effectively ADC bandwidth) be used to collect the HMC661's output without violating its 2ns max hold time even if the ADC itself does not complete the conversion at a 250MHz+ retrigger rate? Essentially creating a lower speed, but dual rank track and hold out of the single rank HMC661.
As an example, why couldn't a HMC661 be followed up with say an AD9265 ~80MSPS converter, which exceeds the performance of nearly any 250MSPS converter on the market? While converting slower than the HMC661's listed 250MHz minimum retrigger time, the AD9265's internal track and hold has a bandwidth of 650MHz implying its actual internal track and hold aperture time is sufficient to capture and re-hold the output of the HMC661 without violating the HMC661's maximum 2ns output hold time. Assuming the two devices are co-triggered with an appropriate ADC delay to make sure the HMC661 has entered hold mode just before the ADC activates the hold mode of its internal track and hold as one would expect. If that type of architecture was created one could theoretically trigger the HMC661/AD9265 setup as slowly as they wanted (say 1MHz) while being assured the HMC661 would never have to keep its hold mode output valid for more than 2ns. Right? Would something like that work?
Due to droop limitations, using a clock rate lower than 250MHz alters the device performance significantly. If you even go further down like 150MHz, droop increases linearly and sample noise increases substantially due to shot noise caused by leakage currents and operating point upsets.
Hi Engineer Zone experts,
I am looking for the answer to the same question as previously posted Jan 5, 2018.
The answer on Jan 18, 2018 was telling us the performance alters significantly due to droop.
Continuing the thoughts, what if the droop happens after the time ADC has completed the conversion.
So, would the droop matter?
Say, the HMC661 is clocked by 150MHz. HMC661 will hold its value for 2nS then droop significantly. The 150MHz ADC has a Sample-and-hold acquisition delay time of 0.5nS. Assuming HMC661 and ADC are synchronized, then the remaining time, even after the 2nS, can droop and it is a “don’t care”, correct?
Please help by sharing your comments, thanks