I have a question concerning the selection of the fundamental or divider mode on the tri-band PLL.
I use a HMC837 with a ref of 50MHz and an output frequency about 2256MHz
I use the default register given by analog and only update the Reg03 and Reg04 to my request.
The PLL locks but not at 2256MHz but at 1128MHz. It seems that the divider mode is active.
In which register the selection of the mode is done?