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AD8304's internal buffer and VPDB not working as expected?

Hello,

I want to integrate the AD8304 into my design. My plan is to build an optical power meter within the range of 1uW to 1mW.

According to the datasheet, a recommended configuration is shown in figure 7 which I have implemented. 

Although this configuration seems to work in the long term it only works for a couple of days. Puzzled by this behavior I took note of some observations over several samples during the last 2 months. Hopefully I can get some support or comments on this issue so I can move on. Otherwise I will appreciate recommendations for a replacement that can be easily implemented.

The observations are the following:

1.- When No buffer enabled, VP = 5 V and no PD current . VLOG varies from 0.9 V to 0.55V after a couple of days. After that period of time, VLOG is stable and VPDB is 0.6V.

2. When Buffer is enabled, VP = 5V and PD current flowing. The inner buffer was configured to provide a gain of 3. For instance a VLOG of 1V, VOUT is 3 V. After one day of operation, VOUT goes up 4.5Volts without no reason. Exploring the why of this situation, I found that VLOG remains stable but VPDB, which went up from 0.6 to 1.5V. Unfortunately, I can no longer use this configuration. This is has been a common behavior over several samples.

My hypothesis is that probably the power supply is not adequate for this application. It features large ripple  and it is not well regulated. It could happen that the AD8304 tries to compensate this power variations internally and then breaks out.

Could you confirm this possibility or advice what other thing could be the cause?.

best regards,

Fausto

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  • Greetings Fausto, 

    Sorry about the delay, as our primary Apps. Engr. for this device is out of the office. Perhaps I could be of assistance: 

    To eliminate power quality uncertainty, a low-noise, well-regulated power supply with +5.0 Volt output is strongly recommended. For the purpose of troubleshooting, this could be a lab-grade bench power supply. 

    Also, its possible that the AD8304 is oscillating, thus creating the observed power supply ripple. Please confirm that the C1, R1 elements are installed as shown in datasheet Figures 1 and 3. 

    Regarding the specific observations:

    1. In the first case with no buffer, Vp= 5V, and no PD current, output voltage should be much closer to 0 Volts, as shown in datasheet Figure 2. The same figure shows that for 0.9V output, input current should be about 3uA, so please check the layout for possible sources of this leakage current into pin 4. Poor PCB layout could cause this, as could PCB contamination such as flux residue or dielectric moisture absorption. In the event of PCB contamination, the cure may be thorough cleaning and hot-air drying or baking of the PCB. Regarding PCB layout, note that Figure 23 shows a guard ring surrounding pin 4 on our factory evaluation PCB, to help reduce current leakage into this pin. 

    2. The Adaptive biasing is intended to optimize performance when the PD internal Rs is around 200 Ohms. If Rs is much higher, the Adaptive biasing does not increase VPDB voltage enough to accommodate the reverse bias requirement for higher optical power (higher current). So for use with high Rs PD's, Adaptive bias should not be utilized. If any doubt, the safest approach is to not use Adaptive biasing, as shown in datasheet Figure 3. 

    Regards,

    Bruce

Reply
  • Greetings Fausto, 

    Sorry about the delay, as our primary Apps. Engr. for this device is out of the office. Perhaps I could be of assistance: 

    To eliminate power quality uncertainty, a low-noise, well-regulated power supply with +5.0 Volt output is strongly recommended. For the purpose of troubleshooting, this could be a lab-grade bench power supply. 

    Also, its possible that the AD8304 is oscillating, thus creating the observed power supply ripple. Please confirm that the C1, R1 elements are installed as shown in datasheet Figures 1 and 3. 

    Regarding the specific observations:

    1. In the first case with no buffer, Vp= 5V, and no PD current, output voltage should be much closer to 0 Volts, as shown in datasheet Figure 2. The same figure shows that for 0.9V output, input current should be about 3uA, so please check the layout for possible sources of this leakage current into pin 4. Poor PCB layout could cause this, as could PCB contamination such as flux residue or dielectric moisture absorption. In the event of PCB contamination, the cure may be thorough cleaning and hot-air drying or baking of the PCB. Regarding PCB layout, note that Figure 23 shows a guard ring surrounding pin 4 on our factory evaluation PCB, to help reduce current leakage into this pin. 

    2. The Adaptive biasing is intended to optimize performance when the PD internal Rs is around 200 Ohms. If Rs is much higher, the Adaptive biasing does not increase VPDB voltage enough to accommodate the reverse bias requirement for higher optical power (higher current). So for use with high Rs PD's, Adaptive bias should not be utilized. If any doubt, the safest approach is to not use Adaptive biasing, as shown in datasheet Figure 3. 

    Regards,

    Bruce

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