Post Go back to editing

AD8304's internal buffer and VPDB not working as expected?

Hello,

I want to integrate the AD8304 into my design. My plan is to build an optical power meter within the range of 1uW to 1mW.

According to the datasheet, a recommended configuration is shown in figure 7 which I have implemented. 

Although this configuration seems to work in the long term it only works for a couple of days. Puzzled by this behavior I took note of some observations over several samples during the last 2 months. Hopefully I can get some support or comments on this issue so I can move on. Otherwise I will appreciate recommendations for a replacement that can be easily implemented.

The observations are the following:

1.- When No buffer enabled, VP = 5 V and no PD current . VLOG varies from 0.9 V to 0.55V after a couple of days. After that period of time, VLOG is stable and VPDB is 0.6V.

2. When Buffer is enabled, VP = 5V and PD current flowing. The inner buffer was configured to provide a gain of 3. For instance a VLOG of 1V, VOUT is 3 V. After one day of operation, VOUT goes up 4.5Volts without no reason. Exploring the why of this situation, I found that VLOG remains stable but VPDB, which went up from 0.6 to 1.5V. Unfortunately, I can no longer use this configuration. This is has been a common behavior over several samples.

My hypothesis is that probably the power supply is not adequate for this application. It features large ripple  and it is not well regulated. It could happen that the AD8304 tries to compensate this power variations internally and then breaks out.

Could you confirm this possibility or advice what other thing could be the cause?.

best regards,

Fausto

  • Hi.

    Moved this question about AD8304 here in RF and Microwave community. would be able to help you.

    Regards.

  • Hello Jinol,

    is there someone else that could help me out on this issue?. jdobler seems to not being online for long time.

    best regards,

  • Sorry for the delay in responding. I'll try to get someone to look at this as jdobler is currently on vacation.

  • Greetings Fausto, 

    Sorry about the delay, as our primary Apps. Engr. for this device is out of the office. Perhaps I could be of assistance: 

    To eliminate power quality uncertainty, a low-noise, well-regulated power supply with +5.0 Volt output is strongly recommended. For the purpose of troubleshooting, this could be a lab-grade bench power supply. 

    Also, its possible that the AD8304 is oscillating, thus creating the observed power supply ripple. Please confirm that the C1, R1 elements are installed as shown in datasheet Figures 1 and 3. 

    Regarding the specific observations:

    1. In the first case with no buffer, Vp= 5V, and no PD current, output voltage should be much closer to 0 Volts, as shown in datasheet Figure 2. The same figure shows that for 0.9V output, input current should be about 3uA, so please check the layout for possible sources of this leakage current into pin 4. Poor PCB layout could cause this, as could PCB contamination such as flux residue or dielectric moisture absorption. In the event of PCB contamination, the cure may be thorough cleaning and hot-air drying or baking of the PCB. Regarding PCB layout, note that Figure 23 shows a guard ring surrounding pin 4 on our factory evaluation PCB, to help reduce current leakage into this pin. 

    2. The Adaptive biasing is intended to optimize performance when the PD internal Rs is around 200 Ohms. If Rs is much higher, the Adaptive biasing does not increase VPDB voltage enough to accommodate the reverse bias requirement for higher optical power (higher current). So for use with high Rs PD's, Adaptive bias should not be utilized. If any doubt, the safest approach is to not use Adaptive biasing, as shown in datasheet Figure 3. 

    Regards,

    Bruce

  • Hello Bruce,

    In the meantime of receiving your reply, I did the following modifications:

    • I employed a well-regulated and low ripple power supply to eliminate power incertitude.
    • I found out that leaving pins 3 and 5 not connected and removing the 10nF capacitor connected to these pins, in the configuration shown in figure 7 of the datasheet, the amplifier section of the AD8304 works. Therefore only R1, C1, CB, RA and RB are present in my current setup. Can you comment on this point?. Why connecting pin 3 and 5 and adding the 10nF makes the circuit unstable?. For instance, VPDB went up from 0.75V  to 1.9V for a 1mA current and output amplifier stops working (the output is saturated or sometimes goes to 0 V) . Also output presented oscillations until reaching saturation.
    • As for the current leakage in pin 4 is understandable since I'm testing on an electronic breadboard whose parasitic currents are of the order of several hundreds of nAs. I will follow your suggestions in the implementation of the PCB so expectations to reduce current leakage to lower values will be fulfilled.
    • As for the VPDB value, In the current setup I measure a value around 0.757V that corresponds to a current of 1mA which corresponds to the optical power I'm applying and to the internal resistance of the photodiode I'm using ( 225 Ohms). So far, the circuit has been working for almost 2 days.

    Just didn't want to give up since this device provides several advantages regarding the design I wan to implement.

    Regards.

    Fausto

  • Greetings Fausto,

    Regarding stability: The 10nF on pins 3 & 5 works in conjunction with the internal series 10k resistor to filter noise on VSUM, and helps keep VSUM at a low AC impedance. VSUM is intended as a guard ring for the input signal. If circuit does not oscillate with 10nF removed, its likely because of stray capacitance to INPT pin, and in this configuration the guard ring will not work well. A better solution would be to install the 10nF, and make the required changes to the stability network, for example C1= 10nF and R1= 75 Ohms should help. Finding the best RC values may require some experimentation. This way the guard ring can also function correctly. The output amplifier should always faithfully amplify the VLOG signal, in accordance with the amplifier gain equation G= (RA+RB)/RB, subject to saturation near the power supply rails.

    Regarding VPDB: Rs= 225 Ohms is a little too high for this device to automatically keep constant back-bias across the PD element. After the oscillation problem is fixed, you may find that measurement range 'flattens out' up at higher optical power levels, because the PD does not have enough reverse bias. If this becomes a problem, the solution would be a PD with lower Rs, or simply do not use the VPDB pin (external bias required). 

    Regards,

    Bruce

  • Hello Bruce,

    Thanks for your reply. I did follow your advice regarding the stability of the circuit. The values of the components are set  to C1 = CB = CPB = 1nF, R=470 Ohm. The optimization was made via an oscilloscope connected to VLOG  and measuring the AC variations (only continuous optical power will be provided to the PD). However these values are adapted to a circuit mount on a  solderless breadboard which provides some stray  capacitance.

    I think once the PCB is made, I should optimize this circuit am I right?

    In the absence of optical power, I get a VLOG of the order of 0.650 V, I suspect it is due to stray capacitance. Could you comment on this?. ( looking at the figure 2 of the data sheet I would say that there is a parasitic current of the order of 200nA)

    As for the VPDB, the maximum current that the PD will generate, based on the input optical power, will be of the order of 1mA. Therefore the voltage provided by the VPDB will be enough for my application.

    best regards,

    Fausto

  • Greetings Fausto,

    Yes, on the final PCB, you should once again check for stability. It's likely that no new changes will be necessary.

    The VLOG= 0.65 V is likely due to leakage current of the PD under dark condition. Check the PD datasheet for this line item.

    Also, check that C1 is a low-leakage type of capacitor. C1 leakage current subtracts from the desired PD input current, which tends to limit the low end of the measurement range.

    Best regards,

    Bruce

  • Hi Bruce,

    Again, thanks fro your reply. It provides a great help.

    I have verified the specs for the photodiode I'm currently using. It states 5nA, which is low compared to the low end of the measurement range I want to measure. For the application I'm considering, I would like to start from 100nA. Although perhaps the dark current of the PD is higher than stated, however I do have differences on the output voltage between having an optical power providing 100nA current flowing in the PD and not having optical power applied on the PD at all.

    I remark some fluctuations on the output voltage in the lower end of my measurement. The fluctuations start disappearing from 10uA upwards. Although I have optimized R1 and C1, these fluctuations can not be removed at lower current values.

    any recommendation?

    As for the parasitic current at the input pin, I removed the photodiode to mimic a high impedance but VLOG remains at the same value. So I don't know what can produce this output. Any other idea?.

    Regards,

    Fausto

  • Greetings Fausto,

    Regarding the fluctuations, it could be C1, either capacitance or leakage resistance changing with respect to time. Please try an improved grade of capacitor for C1. There are both polypropylene film capacitors and polyester film capacitors available. Both offer very high leakage resistance specification. For example: 

    http://www.digikey.com/product-detail/en/kemet/PFR5102F100J11L4BULK/399-7694-ND/

    http://www.digikey.com/product-detail/en/nichicon/QYX1H102KTP/493-3377-ND/ 

    Regarding the offset when PD not connected, it sounds like a leakage path on the solderless breadboard. You might try rearranging the connections such that INPT pin is fully floating, completely away from external circuitry, especially the positive voltages such as Vp, because the circuit is very sensitive to such leakage. For the final PCB layout, be sure to include the guard ring as shown on the demo board layout.

    Best regards,

    Bruce