Hi ADI, for testing purposes, how do I force pin 27 LKDET of the ADF4382, high or low?
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ADF4382
Recommended for New Designs
The ADF4382 is a high performance, ultra-low jitter, fractional-N
phased-locked loop (PLL) with an integrated voltage controlled
oscillator (VCO) ideally...
Datasheet
ADF4382 on Analog.com
Hi ADI, for testing purposes, how do I force pin 27 LKDET of the ADF4382, high or low?
Yes there is a debug mode whereby, if you set the 2 LSBs to binary ‘11’, this should force LD pin high. By default the value is ‘01’ for normal operation.
Yes there is a debug mode whereby, if you set the 2 LSBs to binary ‘11’, this should force LD pin high. By default the value is ‘01’ for normal operation.