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ADF4382 Recommended for New Designs
The ADF4382 is a high performance, ultra-low jitter, fractional-N phased-locked loop (PLL) with an integrated voltage controlled oscillator (VCO) ideally...
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ADF4382 on Analog.com

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Force pin 27 LKDET high or low

		
	
				

			

									
					    johnpritchard
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Sep 14, 2026 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user asked how to force the LKDET pin (pin 27) of the ADF4382 high or low for testing purposes. The final answer indicates that setting the 2 LSBs of the debug register to binary ‘11’ forces the LD pin high, while the accompanying answers suggest methods to force LKDET low, such as removing the reference clock or programming an invalid frequency.
                        	    

                
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Category: Hardware

    		        		            		    
Product Number:  ADF4382  

    		        		    		    

		    		    
		    			

			    
Hi ADI, for testing purposes, how do I force pin 27 LKDET of the ADF4382, high or low?

			

			
									
		                             
                        

    

                                            
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                 Force pin 27 LKDET high or low
                
                                
            

    
    
		


				
				        
        		

			
						
									
												
			
			
                        
                                    
                        
                                                    
                        
            
			            
						
						
			
			
			
			
		


        
        
        
    
					

			





















	

	

					



			


				
	









	
    
	

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Sep 17, 2026 8:33 AM
            
            
						
			            		
    
		
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    Hi,
     
    Pin 27 (LKDET) on the ADF4382 is a lock detect output, not an input. It reflects the PLL lock status (Digital Lock Detect or Analog Lock Detect, depending on the register configuration). 
    If your goal is simply to force the pin state for system testing:
    Force LKDET LOW
    The easiest method is to make the PLL lose lock, for example:
    • Remove the reference clock.
    • Program an invalid frequency.
    • Put the PLL into power-down.
    • Disable VCO calibration.
    In the unlocked state, the Digital Lock Detect output goes LOW.
    Force LKDET HIGH
    You must place the PLL into a valid locked condition:
    • Apply a valid reference.
    • Program a valid output frequency.
    • Wait for calibration and lock completion.
    When the PLL is locked, the Digital Lock Detect output goes HIGH.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
				
				
				
		
		
    
			
		
    
	
    

    

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                on Sep 17, 2026 11:02 AM
            
            
						
			            		
    
		
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    Hi Olim, thanks for the suggestions. I wanted to test the connection to the host controller from pin 27 whether or not the system was actually locked. Therefore I wanted to force the LKDET pin to a wanted state by configuring a suitable regeister. Obviously I can hold the lock detection system in reset, thus forcing pin 27 LOW, by setting the RST_LD bit.
    

    But how can I force the LKDET pin high?
    

    Can I use those reserved bits in reg 0x2D? An old version of the datasheet for the ADF4382A suggests that bit 0 and 1 are LD_O_CTRL. Does that help me? The old datasheet also suggests that bit 3 is PDET_POL. Does this help?
    

    Thanks again
    

    JP
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
				
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Sep 22, 2026 4:46 AM
            
            
						
			            		
    
		
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    Yes there is a debug mode whereby, if you set the 2 LSBs to binary ‘11’, this should force LD pin high. By default the value is ‘01’ for normal operation.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
				
				
				
		
		
    
			
		
    
	
    

    

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