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ADF4382A Recommended for New Designs
The ADF4382A is a high performance, ultralow jitter, fractional-N phased-locked loop (PLL) with an integrated voltage controlled oscillator (VCO) ideally...
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ADF4382A on Analog.com

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Problem reading registers from ADF4382A through SPI

		
	
				

			

									
					    aml94
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Jul 8, 2026 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user encountered incorrect readback values from the ADF4382A PLL on the EVAL-ADF4382A (REV D) evaluation board using both custom C functions and ACE software. The issue was resolved by disconnecting the oscilloscope probes from the test points (TP1 and TP2) and connecting them directly to the P2 connector. However, 3.3V logic with 4-wire SPI mode still exhibits readback issues on the REV D board.
                        	    

                
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Category: Hardware

    		        		            		    
Product Number:  ADF4382A  

    		        		    		    

		    		    
		    			

			    
Hi everyone,




Recently I have been trying to work with ADF4382A an its evaluation board (EVAL-ADF4382A, REV D) both with ACE software and my own C functions and I am having some problems.




At first I was only trying to write and read through the SPI with my own custom C functions and while the writing operations seemed to work pretty well, the reading ones failed as the values read didn't match with the expected ones. I am sure that the registers were written ok because with an oscilloscope I could see the SDIO line change its voltage depending on the configuration of the 0x3D register. I could even achieve the PLL lock at some frequency of my interest. But, unfortunately, when I tried to make a silly read operation following the datasheet instructions, I encountered that the values returned were wrong. I tried to read different registers like 0x0C or 0x0D but instead of returning the POR  values they returned 0x01 and 0x00.


 


I assumed that my code had some mistake coming from a missunderstanding so I decided to use ACE to make some reads and compare the oscilloscope readings with the previous ones. To my surprise, the readings returned the same (e.g. 0x01 from the 0x0C register). This happens in spite of the SPIO line configuration, whether I use 3 or 4 wires, 1.8 or 3.3 V. In the screenshot of the oscilloscope trace that is attached I was working with 4 wires and 1.8V using ACE software. (BLUE = CSB, RED = SCLK, GREEN = SDO, YELLOW = SDIO)


 


I have not much knowledge, but I can see some things that for me seem off:


1- If the PLL is working in 1.8V, why does the logich high of the SDIO line reach 2.65V?


2- Is it normal that the SDO line is stuck at 2.36V when writing the address? Because when performing the reading at logic high it only reaches 1.8V




I have read across EF that there used to be a problem with a SDO resistor with some revisions of the evaluation board, but the bad readings for me also happen in the 3 wire configuration, so it may not be just a SDO problem, right? (see 2nd screenshot, 3wire 3.3V)


 




For me this seems like some kind of electrical problem, but I don't know how could this be when I am working with the EVAL board and the SDP-S controller board. Does anyone have some ideas?




Thank you very much in advance,


Andres

			

			
									
		                             
                        

    

                                            
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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Jul 17, 2026 9:48 AM
            
            
						
			            		
    
		
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    Hi Andrés,
    

    Thank you very much for the detailed follow-up, and no worries at all on the timing. I really appreciate you taking the time to document the root cause. These silly bench-level issues can cost a lot of debugging time, especially when the symptoms look like a firmware or device readback problem at first glance.
    

    For reference, my setup on my side is the following:
    

    

    My setup:

    

    

    

    

    ACE version: 1.30.351.7117 x64
    

    Board: EVAL-ADF4382A / ADF4382A Board
    

    Board revision: REV F

    

    Controller: SDP-S
    

    Power supply: 6 V
    

    Current state: Good

    

    

    On my bench, I saw somewhat similar behavior in the sense that hitting software defaults in ACE made the memory map match the datasheet/register map values, but actual hardware reads were returning 0xFF across the register map. I also checked both 3-wire and 4-wire SPI modes, and even after switching to 4-wire mode, SDO appeared to sit high during the read transaction. I confirmed that CSB, SCLK, and SDIO were showing activity when a read was initiated, but SDO did not appear to toggle during the readback window.
    

    Given your finding, I am going to revisit my own setup and independently confirm whether the 0xFF readback behavior I observed was also measurement-induced, probe-location-induced, or something else in my setup. In particular, I will avoid probing the TP1/TP2 data-line test points and will try probing from the P2 connector as you did. It would not surprise me if this turns out to be another silly scope-probe interaction with the SPI data lines.
    

    I am glad to hear that once the probes were removed from TP1/TP2, ACE was able to read the device correctly, and that you were able to debug your custom C functions successfully. That is a very useful finding, and I agree that it is worth leaving documented for anyone else who may run into the same behavior.
    

    Regarding your remaining note that 3.3 V logic with 4-wire mode still does not appear to behave correctly on the Rev D board, I will continue looking into that. Since 4-wire readback depends specifically on the SDO path, while 3-wire mode uses SDIO for readback, that remaining issue may still point to something specific about the Rev D SDO path, board population, or 3.3 V readback configuration. I will work on getting you a more concrete answer there.
    

    Thanks again for the excellent follow-up and for sharing the final root cause.
    

    Best regards,
     Douglas Plummer
    

    

    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
				
				
				
		
		
    
			
		
    
	
    

    

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  • 
	
    



	
		
	
	



    
	
    
		
    
							
					
    
		
    
		    
		    		    
			
				
									
							        
			
			
			
    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Jul 17, 2026 9:48 AM
            
            
						
			            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    

    

    

    Hi Andrés,
    

    Thank you very much for the detailed follow-up, and no worries at all on the timing. I really appreciate you taking the time to document the root cause. These silly bench-level issues can cost a lot of debugging time, especially when the symptoms look like a firmware or device readback problem at first glance.
    

    For reference, my setup on my side is the following:
    

    

    My setup:

    

    

    

    

    ACE version: 1.30.351.7117 x64
    

    Board: EVAL-ADF4382A / ADF4382A Board
    

    Board revision: REV F

    

    Controller: SDP-S
    

    Power supply: 6 V
    

    Current state: Good

    

    

    On my bench, I saw somewhat similar behavior in the sense that hitting software defaults in ACE made the memory map match the datasheet/register map values, but actual hardware reads were returning 0xFF across the register map. I also checked both 3-wire and 4-wire SPI modes, and even after switching to 4-wire mode, SDO appeared to sit high during the read transaction. I confirmed that CSB, SCLK, and SDIO were showing activity when a read was initiated, but SDO did not appear to toggle during the readback window.
    

    Given your finding, I am going to revisit my own setup and independently confirm whether the 0xFF readback behavior I observed was also measurement-induced, probe-location-induced, or something else in my setup. In particular, I will avoid probing the TP1/TP2 data-line test points and will try probing from the P2 connector as you did. It would not surprise me if this turns out to be another silly scope-probe interaction with the SPI data lines.
    

    I am glad to hear that once the probes were removed from TP1/TP2, ACE was able to read the device correctly, and that you were able to debug your custom C functions successfully. That is a very useful finding, and I agree that it is worth leaving documented for anyone else who may run into the same behavior.
    

    Regarding your remaining note that 3.3 V logic with 4-wire mode still does not appear to behave correctly on the Rev D board, I will continue looking into that. Since 4-wire readback depends specifically on the SDO path, while 3-wire mode uses SDIO for readback, that remaining issue may still point to something specific about the Rev D SDO path, board population, or 3.3 V readback configuration. I will work on getting you a more concrete answer there.
    

    Thanks again for the excellent follow-up and for sharing the final root cause.
    

    Best regards,
     Douglas Plummer
    

    

    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
				
				
				
		
		
    
			
		
    
	
    

    

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