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Problem reading registers from ADF4382A through SPI

Thread Summary

The user encountered incorrect readback values from the ADF4382A PLL on the EVAL-ADF4382A (REV D) evaluation board using both custom C functions and ACE software. The issue was resolved by disconnecting the oscilloscope probes from the test points (TP1 and TP2) and connecting them directly to the P2 connector. However, 3.3V logic with 4-wire SPI mode still exhibits readback issues on the REV D board.
AI Generated Content
Category: Hardware
Product Number: ADF4382A

Hi everyone,

Recently I have been trying to work with ADF4382A an its evaluation board (EVAL-ADF4382A, REV D) both with ACE software and my own C functions and I am having some problems.

At first I was only trying to write and read through the SPI with my own custom C functions and while the writing operations seemed to work pretty well, the reading ones failed as the values read didn't match with the expected ones. I am sure that the registers were written ok because with an oscilloscope I could see the SDIO line change its voltage depending on the configuration of the 0x3D register. I could even achieve the PLL lock at some frequency of my interest. But, unfortunately, when I tried to make a silly read operation following the datasheet instructions, I encountered that the values returned were wrong. I tried to read different registers like 0x0C or 0x0D but instead of returning the POR  values they returned 0x01 and 0x00.

 

I assumed that my code had some mistake coming from a missunderstanding so I decided to use ACE to make some reads and compare the oscilloscope readings with the previous ones. To my surprise, the readings returned the same (e.g. 0x01 from the 0x0C register). This happens in spite of the SPIO line configuration, whether I use 3 or 4 wires, 1.8 or 3.3 V. In the screenshot of the oscilloscope trace that is attached I was working with 4 wires and 1.8V using ACE software. (BLUE = CSB, RED = SCLK, GREEN = SDO, YELLOW = SDIO)

I have not much knowledge, but I can see some things that for me seem off:

1- If the PLL is working in 1.8V, why does the logich high of the SDIO line reach 2.65V?

2- Is it normal that the SDO line is stuck at 2.36V when writing the address? Because when performing the reading at logic high it only reaches 1.8V

I have read across EF that there used to be a problem with a SDO resistor with some revisions of the evaluation board, but the bad readings for me also happen in the 3 wire configuration, so it may not be just a SDO problem, right? (see 2nd screenshot, 3wire 3.3V)

For me this seems like some kind of electrical problem, but I don't know how could this be when I am working with the EVAL board and the SDP-S controller board. Does anyone have some ideas?

Thank you very much in advance,

Andres

Parents
  • Hi Andres,

    (This was meant to be sent out last week but there was some issues with the engineering zone reply for my post)

    Thank you for the detailed description and the oscilloscope captures. Based on your observations, it does appear that SPI writes are being accepted correctly, since the PLL can be configured and achieves lock as expected. The fact that both your custom software and ACE are returning the same unexpected readback values makes this a particularly interesting issue to investigate.

    To help narrow down the root cause, could you provide a few additional measurements and checks?

    1. Digital Logic Level Verification

      • Could you confirm the actual digital I/O voltage rail present on the evaluation board when configured for 1.8 V operation?

      • If possible, please verify that the CMOS logic level configuration has been successfully applied and is not remaining at a different voltage level than expected.

    2. Power Rail Measurements

      • Please measure the 6 V supply rail being provided to the evaluation board and confirm that it is stable and free of significant noise.

      • If accessible, please also provide measurements of the relevant onboard regulator outputs.

    3. Readback Testing

      • Do the incorrect readback values occur immediately after power-up, before any user configuration is applied?

      • Are the returned values always the same (for example, 0x01 from Register 0x0C), or do they vary under different operating conditions?

    4. Additional Oscilloscope Capture

      • If possible, could you provide a zoomed-in capture of a complete read transaction showing:

        • CSB

        • SCLK

        • SDIO

        • SDO

      • A capture centered around an attempted read of Register 0x0C or 0x0D would be particularly helpful.

    5. Hardware Information

      • Can you confirm the exact revision of the EVAL-ADF4382A board and SDP-S controller being used?

    I have already ordered an evaluation board on my side and expect to have it in hand tomorrow. Once it arrives, I will attempt to reproduce the behavior using ACE and perform some readback testing under the same conditions you described. This should help determine whether the issue is related to the evaluation hardware, configuration, or the device interface itself.

    I look forward to your feedback.

    Best regards,

    Douglas
    Associate Engineer, Central Applications
    Analog Devices, Inc.

Reply
  • Hi Andres,

    (This was meant to be sent out last week but there was some issues with the engineering zone reply for my post)

    Thank you for the detailed description and the oscilloscope captures. Based on your observations, it does appear that SPI writes are being accepted correctly, since the PLL can be configured and achieves lock as expected. The fact that both your custom software and ACE are returning the same unexpected readback values makes this a particularly interesting issue to investigate.

    To help narrow down the root cause, could you provide a few additional measurements and checks?

    1. Digital Logic Level Verification

      • Could you confirm the actual digital I/O voltage rail present on the evaluation board when configured for 1.8 V operation?

      • If possible, please verify that the CMOS logic level configuration has been successfully applied and is not remaining at a different voltage level than expected.

    2. Power Rail Measurements

      • Please measure the 6 V supply rail being provided to the evaluation board and confirm that it is stable and free of significant noise.

      • If accessible, please also provide measurements of the relevant onboard regulator outputs.

    3. Readback Testing

      • Do the incorrect readback values occur immediately after power-up, before any user configuration is applied?

      • Are the returned values always the same (for example, 0x01 from Register 0x0C), or do they vary under different operating conditions?

    4. Additional Oscilloscope Capture

      • If possible, could you provide a zoomed-in capture of a complete read transaction showing:

        • CSB

        • SCLK

        • SDIO

        • SDO

      • A capture centered around an attempted read of Register 0x0C or 0x0D would be particularly helpful.

    5. Hardware Information

      • Can you confirm the exact revision of the EVAL-ADF4382A board and SDP-S controller being used?

    I have already ordered an evaluation board on my side and expect to have it in hand tomorrow. Once it arrives, I will attempt to reproduce the behavior using ACE and perform some readback testing under the same conditions you described. This should help determine whether the issue is related to the evaluation hardware, configuration, or the device interface itself.

    I look forward to your feedback.

    Best regards,

    Douglas
    Associate Engineer, Central Applications
    Analog Devices, Inc.

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