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ADTR1107 Power Droop

Thread Summary

The user is developing a system with multiple ADTR1107 FE ICs and is concerned about power droop on the +5V rail during TDD mode. The final answer suggests using a 4.7uF capacitor per ADTR1107 and pulsing the gate instead of the drain to manage the power supply, as seen in the ADAR1000EVAL1Z (STINGRAY) reference design. The accompanying answer confirms that gate pulsing reduces the delta I on the +5V rail, addressing the power droop issue.

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Category: Datasheet/Specs
Product Number: ADTR1107

Hello,

I'm currently developing a system that includes a number of ADTR1107 FE ICs all connected to the same voltage rails. Considering only the +5V rail that feeds the PAs and that one it's supposed to fully turn the PAs on and off in TDD mode I was doing some calculations to see if any extra bulk capacitance is needed for the system to work without significant power droop.

If I consider a max. droop of 5% of the VDD=5V, IDD=370mA and a PRF of 10kHz and D=1/3 I easily end up requiring hundreds of uF per each ADTR1107 which, given the tight space constraints, proves to be quite hard to position in the cell layout.

Do you have any suggestion regarding this topic?

BR,

G.

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