ADTR1107 Power Droop

You might find this reference design useful. 

It consists of 32 x ADTR1107 along with 8 x ADAR1000. In this design, we gave each ADTR1107 a 4.7uF capacitor and powered all 32 devices from a single 5V supply. I don't believe that we looked at the power supply droop in detail. But this system has been widely deployed and used and this has not come up as an issue. The closest thing I could find is Rx to Tx settling time with the input power set to -7dBm (that would be an output power from ADTR1107 of around +13 dBm). This plot is in the dataset 

ADAR1000EVAL1Z Data Set [Analog Devices Wiki]

On the wiki site, you can find more information about the design including a full schematic.

There is one other point that I should make that is probably relevant. In your calculations, are you assuming that you will Turn VDD on during each RF pulse, that is, pulse on the drain? Maybe this is where the large cap numbers are coming from. When using ADTR1107 in a large array, we recommend pulsing on the gate. This means that you always have 5V present at the VDD PA pin. In the reference design the 4.7uF cap that is right at the device acts as a local current reservoir which can re-charge during the Rx phase. 

- Eamon

You might find this reference design useful. 

It consists of 32 x ADTR1107 along with 8 x ADAR1000. In this design, we gave each ADTR1107 a 4.7uF capacitor and powered all 32 devices from a single 5V supply. I don't believe that we looked at the power supply droop in detail. But this system has been widely deployed and used and this has not come up as an issue. The closest thing I could find is Rx to Tx settling time with the input power set to -7dBm (that would be an output power from ADTR1107 of around +13 dBm). This plot is in the dataset 

ADAR1000EVAL1Z Data Set [Analog Devices Wiki]

On the wiki site, you can find more information about the design including a full schematic.

There is one other point that I should make that is probably relevant. In your calculations, are you assuming that you will Turn VDD on during each RF pulse, that is, pulse on the drain? Maybe this is where the large cap numbers are coming from. When using ADTR1107 in a large array, we recommend pulsing on the gate. This means that you always have 5V present at the VDD PA pin. In the reference design the 4.7uF cap that is right at the device acts as a local current reservoir which can re-charge during the Rx phase. 

- Eamon