ADTR1107 Power Droop

Indeed, if we stick to gate pulsing the +5V rail is only seeing the delta I of the PA's drains being turned on and off when performing the TRX transition. Thanks for the prompt answer!

On second thought, after reviewing the timing sequence for the ADAR+ADTR combination, when switching from RX to TX the VDD rail is still seeing the full IDDq growing from 0A to, say, 370mA, and that scales with the number of ADTR deployed. If one assumes the PRF is higher than the SMPS bandwidth then the bulk capacitance needs to sustain the drain for the whole D/PRF time, no matter whether it's the drain or the gate being pulsed.

By plugging the values above in the usual C=dI*dt/dv equation gives, for example, that a 4.7uF per device lets the VDD drop by 50% thus introducing a significant AM (and possibly PM) modulation in the first part of the pulse. Now, I trust the hardware over my calculations, but I'd still like to get my modeling of this effect straight, perhaps I'm missing something?

Ping? This forum software is atrocious, I got a notification stating the discussion is awaiting for my follow-up...

I simulated the turn on behavior in LT Spice by switching in and out a 14 ohm load resistor (5V supply 350 mA of VDD current). I am not seeing massive droop on the VDD line. What we do see is that there is droop on the resistor voltage and current if you introduce source resistance to the power supply. Note that in the real application, if you are gate pulsing, there is not switch in the drain path. For the purposes of simulation, I have an ideal switch and a load resistor the mimic the resistance of the VDD pin changing as you take the gate voltage from pinch-off to drain turn on. 

Eamon 

ADTR1107 Turn On.asc