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ADRF6821 - Soft Reset function - Reg 0x0 / 0x1 Description

Thread Summary

The user asked about managing the SOFT RESET bits in the ADRF6821's first two registers. The final answer indicates that the SOFTRESET and SOFTRESET_ bits in Reg0 should be toggled simultaneously (1 for reset), while the SOFT RESET bit in Reg1 should not be used. The datasheet will be updated to reflect this, but no timeline is provided.
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Category: Datasheet/Specs
Product Number: ADRF6821

Hello. 

Reading the ADRF6821 datasheet, we have few questions regarding two first registers. 
 


The first is about the SOFT RESET. There are 3 bits to be controlled, but we did not find any description how to manage them. 
Could you explain how they should be triggered? Do we need to write an one of them and it will be cleared automatically or we need to clear it with another write? 

The second is about doubled bits in Reg0. Should we write them simultaneously? 

It would be nice if you can describe briefly how to use all bits in Reg 0 and Reg1.

Thank you in advance.

Best regards, Pavel