Hi Teams,
We are facing a problem about the SPI programming in FPGA to the chip ADMV8818 mounted on our product.
Questions are:
1. For single instruction SPI mode, we programmed : 0x0000 with 3C and 0x0001 with 80, then filter settings as follows (using switch 1):
The SPI signals (625kHz) transfered but the chip didn't respond to right frequency (here we expected 2GHz (verified with evaluation board) but centered at 3.3GHz).
2. For SPI streaming mode, we reproduced the same sequence as the evaluation boards (ACE software + SDP-S + EVAL-ADMV8818) as follows:
- Why there is a writing action to 0x000A which is not listed in the register map ?
- Should we strictly follow the same sequence/timming (eg. ~10ms at the reset step, then 1ms between different segments) ? If not, is there another sequence we need to follow if we use only normal operation without fast latch mode?
- If we dont need fast latch mode, should we still programm all registers from 0x0100 LUT0_SW to 0x01FF ? If not, which are the registers to program from powering up the chip ?
We really appreciate your reactivity on this because we are at prototype phase and the delivry time is very soon.
Thanks in advances for your help.
XL
