Category: Datasheet/Specs
Product Number: ADRF5730
I am limited to a 1us resolution in my configuration. I am therefore intending on having a single data bit length of 10 us (tcs and tch of 5us each) and a tsck of 10us, where the CLK is high for 5us with the tch. Timing specification denotes a typical control hold time of 20 ns with no maximum designated. Are there any issues in slowing the serial period (tsck), control setup time (tcs), and control hold time (tch) to the microsecond range in this manner for this component?
Edit Notes
Wrong tsck entered in original post[edited by: Leo13 at 5:10 PM (GMT -5) on 8 Jan 2026]
