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AD8302 Magnitude/Phase Output Saturation

Thread Summary

The user designed a custom 4-layer PCB based on the AD8302-EVALZ schematic to measure phase difference between two sinusoidal signals (17 MHz-150 MHz, 300-400mVpp @ 50 Ohms). The IC did not function correctly, showing 0.9V on Vmag and 1.8-2V on Vphase outputs. The issue was resolved by soldering the IC using a hotplate at 230°C, as the DC bias at the inputs was collapsing when soldered with a soldering iron or hot air. The final answer suggested checking for shorts caused by solder paste bleeding onto the IC pins due to the ground plane proximity.
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Category: Hardware
Product Number: AD8302
I have designed a custom 4-layer PCB based on the AD8302-EVALZ schematic, but I am facing a specific issue with the Phase Output. My goal is to read the phase difference between two sinusoidal signals (17 MHz-150 MHz, around 300-400mVpp @ 50 Ohms). The eval boards that I have work without any problem, but when I solder an IC to the PCB, it doesn't work. I confirmed with an oscilloscope that the signals are present at the IC pins (after the coupling capacitors). I am reading 0.9V on Vmag and 1.8-2V on Vphase outputs. There are no short-circuits or cold joints that I can see.
I think the chip is not damaged, I can read 1.834V Vref voltage. My 4-layer PCB's stackup is SIG/GND/GND/SIG, both input signal traces matched to the 50 ohm impedance. 
  •  I see a few potential issues with your circuit that may or may not be causing the problem. I assume that you are seeing fixed dc levels at the magnitude and phase outputs (0.9 on VMAG and 1.8 to 2 V on VPHS. And you were expecting both signals to be moving because they are at different frequencies (that should at least cause the VPHS signal to be changing).

    1. The OFS caps are set 1nF. That sets an input high-pass corner frequency of 2 MHz. If your lowest input frequency is 17 MHz, that is probably ok but I might make that cap a bit bigger to move the corner a little further away from 17 MHz.
    2. There is no need for the resistor on VREF. It's not doing any harm and is unlikely to be related to the problem you are seeing. But it's unnecessary.
    3. The 10 nf caps on MFLT and PFLT set an output low pass corner of 4.8 KHz. If you are looking to see instantaneous changes in phase between the two input signals, I would say that this corner frequency is too low.  
  • I've not heard back from you. Let me know if you need additional help. Otherwise, I'll close this out. 

  •   thank you for your response, I found out that there is a problem in DC bias at the inputs. I should see around 3.2V bias, but I sometimes I see that bias, and after a few seconds, it just collapses. (Vdd is 3.3V, and the datasheet says there should be around 3.2V bias). So I soldered a new PCB with a hotplate around 230 degrees celcius and the problem is fixed. My problem right now is that if I try to solder the IC with a soldering iron or a hot air it just doesn't work. I am under the recommended temperature on the datasheet (under 300 degrees celcius). I don't apply too much heat on pins of the IC. So I don't really see the reason why this happens.

  • It's hard to know what is going wrong here. This device should not be difficult to solder as it has leads and no slug on the underside. I double checked this; while I don't have a device at hand, the documentation suggests that this is a 14- pin  TSS0P without an exposed pad.  If I'm interpreting your layout correctly, you appear to have a large area of ground plane under the device with vias. While this is not necessarily a bad thing, I'm wondering if the ground plane's proximity to the device's pins is causing shorts. If you are putting solder paste on the ground plane area under the device, I would remove that because it has nothing to attach to. This may cause it to bleed on to the pins. 

  • So, no short circuits occur during soldering; I check it afterwards with a multimeter. I would describe the AD8302 as an integrated circuit that requires very precise soldering because I haven't seen another integrated circuit in a TSSOP-14 package that causes this many problems. I appreciate your help.