ADRF5050 SP4T – Partial Port Switching Failure when LS Pin is Asserted before VSS

Hello ADI Team,

We are using the ADRF5050 SP4T switch across multiple boards and are facing an issue where only some of the RF ports switch correctly, while other ports do not respond.

We are using two ADRF5050 devices connected together and controlling both devices using only two digital control lines (the control pins of both devices are shorted together).

Power-Up Sequence Used

1. VDD = +3.3 V

2. VSS = −3.3 V

3. Then the digital control lines

LS Pin Configuration

• LS pin of Switch-1 is tied permanently to GND

• LS pin of Switch-2 is tied permanently to +3.3 V

Because of this, when +3.3 V is applied, the LS pin of Switch-2 is already logic HIGH before VSS (−3.3 V) is present.

Observed Behavior

• Some RF paths switch correctly.

• Some RF paths never switch or behave inconsistently.

• The failures are not repeatable across all boards.

Question

Can asserting the LS pin HIGH before the VSS rail is established cause internal damage or latch-up in the ADRF5050?
Is this an invalid bias condition and the likely root cause for the partial port switching failures we are seeing?

Any guidance on the correct sequencing and LS pin handling would be greatly appreciated.

Thank you.