Hello,
I have never have the software-knowledge or use ADIsimPLL, so I would appreciate any advice you could give me.
[Background] Customer is designing a local signal generator using ADI's ADF5355 synthesizer.
It is using ADIsimPLL due to configure the chip and to design the off-chip loop filter.
[Question 1] ADIsimPLL does not have an option equivalent to the divided REF signal input that can be configured in ACE.
How should they address this? As a block, should they think of it as something external to the synthesizer core and use the divided signal as the REF input?
[Question 2] The chip itself is handled by ACE, and the loop filter is handled by ADIsimPLL, so we are unable to perform a comprehensive simulation. Is there another tool that connects the two? Or is it possible to address this issue using the existing ACE or ADIsimPLL?