The lock detect does not drop to zero when I release the frequency.

Hi,

sorry for getting back to you so late. For some reason, I received a notification of your posting only today. In the future, you should post in Clock and Timing section. Maybe I'll get a faster notification.

I have to tell you I never played with the HMC3716. I played for example with the HMC4069, which is very similar. The specification of the HMC4069 LD pin is identical with the HMC3716 LD specification. The 1K pull up is on both eval boards. The HMC4069 has also a LED circuit attached, but in my tests, I was never able to turn it on.

My approach to playing with these HMC PFD products is to try to reproduce this figure from the HMC3716 data sheet:

This kind of figure may be obtained only by setting the oscilloscope with 20 MHz bandwidth, which distorts the real outputs of the chip. My recommendation is to disable this filtering and reduce the time scale, so you can see the real LD behavior in your particular test.

In my testing of the HMC4069, I had to make the PFD inputs  (REF=50 MHz, VCO=100MHz because it was then divided by 2) locked in a zero delay to a common reference into a DPLL to obtain LD high at around 4.8V.

Then I introduced a 1 ns phase shift into VCO clock and I got a small variation from 4.8V of LD. So the LD was not anymore constantly 4,8V, but would not go down to 0V either.

At 6 ns phase shift of VCO, LD variation happened at a lower level:

I had to go to 19 ns phase shift to get LD stably low at around 0.3V:

Bottom line: I doubt what you see on the scope is the real behavior of LD. Most likely you have a mix of the situations I presented above for the HMC4069 and at least on some portion of that period of time, LD has moments in which it goes to Low levels.

Petre

Hello,

Sorry for the delay in replying, but I have been out of the office.

Firstly, thank you for your reply, but I think there has been a misunderstanding about what I want to observe and the reason for my question.

I don't quite understand what you mean when you mention the ‘x ns’ VCO phase shift. But in my case, I want to use the LD to see how long it takes to switch from one frequency to another (which should be in the order of ns).

When I observe the LD while locked to a frequency (e.g. 10 GHz), I can clearly see those 5V, and if I unlock completely without any other change occurring, just unlocking, I see the LD at 0V.

My problem is that when I am locked to a frequency (e.g. 10 GHz) and the LD is at 5V, and I perform the operations mentioned above with my FPGA to lock onto another frequency (e.g. 11 GHz), that change is ns and, observing the lock with the LD, I see that it goes from 5V locked to unlocked, but it does not drop completely to 0V; instead, it drops to about 3.5V and recovers to 5V, indicating that it is locked.

Therefore, I would like to know why the LD does not drop to 0V. Is the lock change too fast? Does the LD of the HMC3716 not work properly when there are consecutive lock changes? Malfunction?

I also have some difficulty interpreting my signal when it can be considered blocked in such a short time, so I would like to know when the block detection signal can be considered blocked, whether when it fully recovers to 5 V or when it has recovered to 50% of the increase or something similar.

Thank you very much in advance. I hope my question is now clearer.

Kind regards,

Marcos

this issue has been taken private

Petre