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ADIsimPLL "chip" noise model

Category: Software
Product Number: ADF41513
Software Version: 5.80.01

Hello,

the total phase noise of a PLL consists of contributions of the reference, the VCO, the loop filter and the chip.

All these contributions are plottet in ADIsimPLL to show how the final phase noise is derived.

In the "Help" tab a block diagram of the Phase noise model is given:

Dusting off my old control systems knowledge, it is quite easy to derive how each noise component is shaped.

For the VCO, the output noise would be:  S_{VCO}=n_v(s)*\lvert\frac{1}{1+G(s)}\rvert^2 where nv(s) is the noise of the VCO as can be seen in the datasheet.

Equally, one should be able to derive the noise of the "chip" like this. However, I am unable to find the nPD(s) as is shown in the block diagram.

How is the nPD(s) derived in ADIsimPLL (e.g. in my case I am interested in the nPD(s) for the ADF41513)?

Many thanks!