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Bias and power up LE VS VDD

Thread Summary

The user inquires about using the ADRF5474 in direct parallel mode with Vss at -3.3V, Vdd and LE tied to +3.3V. The support engineer confirms that this bias sequencing (Vss, Vdd/LE, then digital bits) is acceptable and will work fine.
AI Generated Content
Category: Hardware
Product Number: ADRF5474

Hi,

I want to use the ADRF5474 in direct parallel mode.

Doing so, I want to feed Vss to -3,3V, Vdd  and LE physically tied together to +3,3 V,

so bias sequencing will be: Vss, VDD and LE and after digital bits

Are there any consequences?

Thanks

Andrea

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