Hello,
We have implemented the following circuit with AD8309. We intend to obtain the Vlog of the input signal in the range of 60MHz to 66MHz at the center frequency of 63MHz. The input signal is as follows:

The corresponding output signal is as follows:

The circuit that we have used is as follows & the inductor & capacitor values used in the front end are corresponding to 60MHz:

We had the following questions:
a. The output of the log amplifier has a DC offset. Theoretically this should exist, but this offset in our circuit is high (1V). Is this normal ? If not, are there any techniques to reduce it ?
b. The graph provided in the figure 8 of the AD8309 datasheet of RSSI output versus input level in dBm shows the output ranging from 2.4V for 20dBm to about 0.4V for -90dBm. Does this consider the DC offset or is it a peak-to-peak measurement? We were able to get similar graph if we consider the DC offset as well.
Request you to provide some suggestions on the above as this is required for a customer project.
With Regards,
ARK

