HMC542BLP4E Digital Attenuator Control Issues with 3.3V Microcontroller

Are you able to capture the digital streams on a multi-channel oscilloscope (CLK, LE, Resetbar and data)? Also if you continue to clock beyond the 8 cycles, can you check to see if data is coming out of Serial Out?

I think that the image you provided is from the screen of the logic analyzer. It would be good to put some oscilloscope probes down on pins 19,20, 21,22 and 24 to see the signals that are hitting the chip. 

In the picture, I see eight clock pulses (I assume that these drive pin 21 (Shift Clock). I also see a logic high signal that goes low after the rising edge of the sixth pulse and goes back high after the rising edge of the eight pulse. What pin is this driving? If this is the Latch Enable signal, it should be low during the eight clocks and should pulse high after the eight rising edge of the clock (it only takes six bits to set the attenuation but you need to write two dummy bits to make it an 8-bit write. 

I assume that one of the other traces is the data line which is either all high or all low. 

The sequence you describe is correct (eight clocks followed by a low-to-high to low pulse on Latch Enable). But the image from the logic analyzer showed something different (eight clock cycles with a negative going pulse (not sure what pin it was driving) during the last two clock cycles). 

Regarding whether the device is damaged, that is always a possibility. Check the current flowing into the VCC pin, it should be around 2.8mA. If it is very different from this number (say 0.5mA to 10mA), that would be an indicator that the part is damaged. 

Closing out this support request as I've not hear back from you.