Write to TX RAM Memory while in RX Mode

Similar to the RAM, is it possible to write to the SPI registers with new data while TX or RX?

For example, say the BFIC is transmitting and receiving beam data 1. While the BFIC is doing that, could I write to the SPI/control registers (0x01-0x01B, 0x01C, 0x027) beam data 2, without interrupting the transmission/reception of beam data 1 (the TR pin is toggling as needed)? Once the BFIC is done transmitting/receiving, I would toggle TX_LOAD, and after a few cycles toggle RX_LOAD (or LDTX_OVERRIDE, LDRX_OVERRIDE). To my understanding, beam data 2 moves from SPI/control registers to working registers, and once in the working registers, the RF subcircuits change as instructed. 

In other words, I would like beam data 2 in the SPI/control registers ready to go shortly after beam 1 is complete (so then all I would have to do is toggle TX_LOAD and RX_LOAD, and resume toggling TR). 

Similar to the RAM, is it possible to write to the SPI registers with new data while TX or RX?

For example, say the BFIC is transmitting and receiving beam data 1. While the BFIC is doing that, could I write to the SPI/control registers (0x01-0x01B, 0x01C, 0x027) beam data 2, without interrupting the transmission/reception of beam data 1 (the TR pin is toggling as needed)? Once the BFIC is done transmitting/receiving, I would toggle TX_LOAD, and after a few cycles toggle RX_LOAD (or LDTX_OVERRIDE, LDRX_OVERRIDE). To my understanding, beam data 2 moves from SPI/control registers to working registers, and once in the working registers, the RF subcircuits change as instructed. 

In other words, I would like beam data 2 in the SPI/control registers ready to go shortly after beam 1 is complete (so then all I would have to do is toggle TX_LOAD and RX_LOAD, and resume toggling TR).