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About HMC561LP3 Biasing Circuit design

Category: Hardware
Product Number: HMC561LP3

Hi, ADI team:

I'm planning to use the HMC561LP3 to design a frequency multiplication circuit.

When designing the bias circuit, I carefully read the document linked below and found two options for VDD/VGG biasing.

I'm currently leaning towards Figure 2: Fixed gate voltage biasing.

https://www.analog.com/media/en/analog-dialogue/volume-57/number-4/active-biasing-solution-for-phemt-power-amps.pdf

I have some questions about fixed gate voltage biasing:
1. What are the effects of not using the HMC561LP at the optimal bias point? Is it okay to just use the datasheet's Vgg = -1.7V, Vdd = 5V?
2. Does the optimal bias point vary significantly between different HMC561LP3s?

Thanks.

  • Hello Applo168,

    To answer you inquiry on HMC561LP3, 

    1. operating the device outside spec will affect the device performance. It is always best to use specified VDD and VGG levels (current levels) in the DS. 

    2. It may vary form part to part, but as suggested in the DS, you may adjust the VGG levels from -2V to -1.2V to achieve an IDD of 98mA.

    Kind Regards,

    Michelle