Category: Software
I encountered some issues when trying to synchronize two ADF4368 chips and hope to get your help. I now want the phase difference between the outputs of the two ADF4368 chips to be consistent every time they are powered on.
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First of all, the phase difference of the input reference clocks is equal. However, when I use the SYNC pin for synchronization, every time I send a synchronization pulse signal through the FPGA, the phase difference of the clock signals locked and output by the two ADF4368 chips changes, and they cannot be synchronized.(The trace lengths are not equal, but they should not affect the phase difference after synchronization)
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When I use EZSYNC for synchronization, according to the steps in the manual, after the two ADF4368 chips are locked, I first write to the synchronization register, then turn off the reference signal and turn it on again. But even so, the phase difference of the waveforms locked and output by the two ADF4368 chips still changes each time.
Could you please give some suggestions? What might be the cause of this situation? Is it a problem with my operation, or are there other factors that I haven't taken into account?